SBAU462 June 2024 PCM1809
The format of the audio data and the operating mode of the ADC are controlled by the following pins: MD0,MD1, MSZ, and FMT0. These signals are referenced to IOVDD and can be set to high (1) or low (0). If no shunt is installed, then a 47kΩ pulldown resistor sets the pin low so that the ADC remains in a defined state. Table 3-1 shows the header numbers and the pin functions and Table 3-2, Table 3-2 and , Table 3-2 show the possible modes and output formats. The MSZ pin selects whether the device is a controller or a target on the audio bus. When MSZ is pulled high, the device is in controller mode and MD1 becomes an input for MCLK. A shunt connecting J19 to the center pin of J18 routes the MCLK signal provided on J8 to the MD1 pin on the ADC to allow for easy interfacing with audio measurement equipment.
| Designator | Function |
|---|---|
| J1 | Differential line/mic input 1 |
| J2 | Differential line/mic input 2 |
| J4 | MICBIAS Selection |
| J5 | IOVDD-SYS voltage Selection (1.8V or 3.3V) |
| J6 | +5V input |
| J7 | AC-MB Connector |
| J8 | Audio Serial Interface header |
| J9 | Connect AVDD to onboard 3.3V regulator |
| J10 | Connect IOVDD to onboard regulator |
| J11 | Connect MICBIAS to onboard MIC2 |
| J12 | Connect MIC2 OUT+ to ADC IN2P |
| J13 | MSZ select |
| J14 | Connect MICBIAS to onboard MIC1 |
| J15 | Connect MIC1 OUT+ to ADC IN1P |
| J16 | Connect MIC1 OUT- to ADC IN1M |
| J17 | MD0 select |
| J18 | MD1 select |
| J19 | MCLK to MD1 |
| J20 | FMT0 select |
| J21 | Connect MIC2 OUT- to ADC IN2M |
| J22 | IN2M capacitor bypass |
| J23 | IN1P capacitor bypass |
| J24 | IN2P capacitor bypass |
| J25 | IN1M capacitor bypass |
| MD0 Modes | ||
|---|---|---|
| MD0 | MSZ (0 = Target, 1 = Controller) | MD0 Functional Mode |
| 0 | 0 | Linear phase filters are used for the decimation in target mode. For controller mode, the device always use linear phase filters for the decimation. |
| 0 | 1 | System clock with frequency 256 × fS connected to the MD1 pin as MCLK. |
| 1 | 0 | System clock with frequency 512 × fS connected to the MD1 pin as MCLK. |
| 1 | 1 | Low latency filters are used for the decimation in target mode. For controller mode, the device always use linear phase filters for the decimation. |
| MD1 Modes | ||
|---|---|---|
| MD1 | MSZ (0 = Target, 1 = Controller) | Functional mode |
| X | 0 | Target mode |
| MCLK | 1 | MCLK input in controller mode |
| Audio Output Data Format | |
|---|---|
| FMT0 | Audio Serial Interface Format |
| 0 | 2-channel output with inter IC sound (I2S) mode |
| 1 | 2-channel output with time division multiplexing (TDM) mode |
All hardware pins are tied low by default, placing the device in target mode with a linear phase filter and 2-channel I2S audio output. For more information on the operating modes of the PCM1809 device, see the PCM1809 Stereo Channel, 102dB Dynamic Range Audio ADC data sheet.