SBOA097B June   2004  – May 2015 INA132 , INA146 , INA152 , OPA2205 , OPA2277 , OPA277 , OPA301 , OPA335 , OPA364 , OPA4205 , OPA725 , TLV2341

 

  1.   High-Voltage Signal Conditioning for Low-Voltage ADCs
    1.     Trademarks
    2. 1 Introduction
    3. 2 Circuit 1: The Modular Approach
    4. 3 Circuit 2: Single-Supply/Single-Port Approach
    5. 4 Circuit 3: Difference Amp Approach
    6. 5 Circuit 4: Differential Input with INA146
    7. 6 Circuit 5: Differential Input Modular
    8. 7 Voltage References and Ranges
    9. 8 References
  2.   Revision History

Circuit 2: Single-Supply/Single-Port Approach

Figure 3 shows a circuit that is attractive to designers who are limited to a single low-voltage supply. The proper selection of biasing components enables both the attenuation and level-shifting functions to be accomplished in one stage.

single_supply_single_part_sboa097.gifFigure 3. Circuit 2: Single-Supply/Single-Part

The following series of formulas defines the relationship of the bias components:

Equation 2. R1 = R3
Equation 3. R2 = R4
Equation 4. Eq04_R1R2_sboa097.gif

Circuit 2 uses the following values:

  • VOUT = 3V
  • VIN = 20(±10)V = V1
  • R1 = R3 = 20.0k 1%
  • R2 = R4 = 3.01k 1%
  • REF1V50 = midpoint of ADC full-scale input range.

This architecture is much more compact than the modular solution of Circuit 1; however, it does rely on tight component tolerances, and does not offer either simple adjustment or filter insertion options. The DC sweep plot of Circuit 2 is shown in Figure 4. Note the large common-mode voltage swing at node N1 and the rail-to-rail output range. These two requirements make the OPA364 the best choice. Also, note the output clamping action of the OPA364, which ensures that the ADC output is not overdriven. This design can be used with input voltages far outside the power-supply rails, though designers need to pay attention to the power dissipated in R3 and the input common-mode voltage limitations of the operational amplifier.

DC_sweep_of_circuit_2_sboa097.gifFigure 4. DC Sweep of Circuit 2