SBOA382A July 2021 – October 2021 INA300-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the INA300-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the INA300-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the INA300-Q1 data sheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- TA = -40°C to +125°C
- VS = 2.7 V to 5.5 V
- VIN+ = 12 V
Table 4-2 Pin FMA for Device Pins Short-Circuited to
Ground
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| IN+ | 1 | In high-side configuration, a short from the bus supply to GND will occur. High current will flow from bus supply to ground. In low side configuration, input pins are shorted. | B |
| IN- | 2 | In high-side configuration, a short from the bus supply to GND will occur. High current will flow from bus supply to ground. In low side configuration, normal operation. | B for high-side; D for low-side |
| LIMIT | 3 | ALERT output is stuck low. | B |
| ENABLE | 4 | Device is disabled. | D if ENABLE=GND by design; C otherwise |
| ALERT | 5 | ALERT output is stuck low. | B |
| LATCH | 6 | If intended connection is not GND, functionality will be affected. | D if LATCH=GND by design; C otherwise |
| DELAY | 7 | If intended connection is not GND, functionality will be affected. | D if DELAY=GND by design; C otherwise |
| GND | 8 | Normal Operation. | D |
| VS | 9 | Power supply shorted to ground. | B |
| HYS | 10 | If intended connection is not GND, functionality will be affected. | D if HYS=GND by design; C otherwise |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| IN+ | 1 | Differential input voltage is not well defined. | B |
| IN- | 2 | Differential input voltage is not well defined. | B |
| LIMIT | 3 | Comparator threshold is not defined. | B |
| ENABLE | 4 | Device mode is not defined. | B |
| ALERT | 5 | ALERT can be left open. | C |
| LATCH | 6 | ALERT pin mode is not defined. | B |
| DELAY | 7 | If intended connection is not OPEN, functionality will be affected. | D if DELAY=OPEN by design; C otherwise |
| GND | 8 | GND is floating. Output will be incorrect as it is no longer referenced to GND. | B |
| VS | 9 | No power supply to device. | B |
| HYS | 10 | If intended connection is not OPEN, functionality will be affected. | D if HYS=OPEN by design; C otherwise |
Table 4-4 Pin FMA for Device Pins Short-Circuited to
Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| IN+ | 1 | IN- | Input differential voltage=0V. | C |
| IN- | 2 | LIMIT | In low-side configuration, ALERT output is stuck low; In high-side configuration, device damage if common mode voltage is greater than 6V. | C for low-side; A for high-side |
| LIMIT | 3 | ENABLE | ALERT output may be stuck low, high or become unpredictable. | B |
| ENABLE | 4 | ALERT | ALERT output may become unpredictable. | B |
| ALERT | 5 | LATCH | ALERT output may become unpredictable. | B |
| LATCH | 6 | DELAY | ALERT output may be transparent, latched or become unpredictable. | B |
| DELAY | 7 | GND | If intended connection is not GND, functionality will be affected. | D if DELAY=GND by design; C otherwise |
| GND | 8 | VS | Power supply shorted to GND. | B |
| VS | 9 | HYS | If intended connection is not VS, functionality will be affected. | D if HYS=VS by design; C otherwise |
| HYS | 10 | IN+ | In low-side configuration, HYS pin is stuck low; In high-side configuration, device damage if common mode voltage is greater than 6V. | C for low-side; A for high-side |
Table 4-5 Pin FMA for Device Pins Short-Circuited to
supply
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| IN+ | 1 | In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. | A for High side; B for low side |
| IN- | 2 | In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. | A for High side; B for low side |
| LIMIT | 3 | Alert output is stuck high. | B |
| ENABLE | 4 | Device is enabled. | D if ENABLE=VS by design; C otherwise |
| ALERT | 5 | Power supply could be shorted to GND though this pin. | A |
| LATCH | 6 | If intended connection is not VS, functionality will be affected. | D if LATCH=VS by design; C otherwise |
| DELAY | 7 | If intended connection is not VS, functionality will be affected. | D if DELAY=VS by design; C otherwise |
| GND | 8 | Power supply shorted to GND. | B |
| VS | 9 | Normal operation. | D |
| HYS | 10 | If intended connection is not VS, functionality will be affected. | D if HYS=VS by design; C otherwise |