SBOA411 December 2020 INA3221-Q1
The failure mode distribution estimation for INA3221-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| ADC output bit error | 15% |
| ADC gain out of specification | 15% |
| ADC offset out of specification | 15% |
| Communication error | 15% |
| Register bit error | 10% |
| ADC MUX select error | 10% |
| Critical – false trip or failure to trip | 5% |
| VPU – false trip or failure to trip | 5% |
| Warning – false trip or failure to trip | 5% |
| TC – false trip or failure to trip | 5% |