ADC resolution creates a similar challenge to that of acquisition time, but on the opposing axis of quantization. When analog information is digitized, quantization error is often a primary source of error, and the magnitude of this error becomes smaller as resolution increases. However, as the error target is now smaller, the ADC is further challenged to settle to a more precise value within the acquisition time of the device. Quantization Error as a Percentage of FSR provides a quick glance at quantization error for various common ADC bit resolutions.

Because of this relationship, as the resolution of the ADC is increased, the amount of settling time needed is increased in turn.