Latch ups (LU) are low-impedance pathways between Vs and GND, which dramatically increases supply current and can easily damage the device through sustained heating. Although latch ups do not always cause damage and can be removed by cycling power.

Latch ups are possible in all ICs that are CMOS or BiCMOS based or use junction isolated processes because there exist inherent, lateral parasitic transistors and diodes formed by PN junctions from the fundamental use of NMOS and PMOS transistors.

The three ways to latch up are overvoltage, current injection, and fast transient. These events can lead to the inadvertent activation of ESD cells during normal device operating conditions. If an ESD cell is sufficiently triggered by EOS or fast edge transient, then this can result in the flooding of carriers from ESD cell into the device substrate, which then can cause a latch up.

Most latch ups are due to ESD cells or parasitic pathways turning on. An ESD cell is a tank of carriers and when there is a trigger at input, the tank of carriers can spill over the layout and substrate.

Latch ups are mitigated in ICs by using guard rings. Guard rings act as carrier sinks to prevent carriers from entering the device substrate. If there are too many carriers, latch ups can go under or over guard rings. All ESD cells can have their own guard rings.

Guard rings however can only work properly when the supply pins are low-impedance and the decoupling capacitance is sufficient. Thus, amplifiers can become more susceptible to latch up when basic layout techniques are not followed.

The Latch-up, white paper describes the theory and practice of IC latch up if more information is desired.