For the most part, the basic layout techniques mentioned above are going to negate risks from EMI induced latch up at VS; however, for excessive noise coupling is always good to follow these additional layout techniques as much as possible to reduce noise into signal.

1. Use shortest and widest possible traces for input pins.
2. Use multiple vias (or larger vias for plane connections).
   1. Use thinner dielectric spacing between top layer and plane to reduce via inductance.
   2. Adding more capacitors in parallel can reduce ESL and improve filtering; however, for best practice, the capacitors are all the same value as most ceramic capacitors (of a single size) manufactured today can have the same impedance regardless of the specified capacitance. Thus, trying to use multiple capacitors of differing capacitance in parallel can create unpredictable resonances.
3. Use LC or PI filters at VS pin to further attenuate noise.
4. Shield or guard sensitive traces with ground traces or pours and vias to create vertical shield walls.