These applications have two different risks: Electromagnetic Interference (EMI) induced noise and EMI induced latch up. Obviously, a latch up is a more serious outcome compared to elevated signal noise; however, the recommended best layout practices to mitigate both risks are the same.

EMI noise does not sound risky, but when in combination with bad layout practices, EMI noise can increase susceptibility of a CSA latch up, specifically at V_S pin. Simple layout techniques can completely negate this risk. The reason for this goes back to the guard rings discussed in Section 2.3 and how internal ESD guard rings help prevent latch ups by absorbing excess carriers before the ESD guard rings can spill out to the substrate. Simply put, proper layout is needed to make sure guard rings operate as expected and keep latch up risk low.

Fast and large voltage or current switching traces from motors or other switching FETs are the main culprits of EMI noise. Thus, VS pin can become more susceptible to EMI coupling when VS trace is long and goes around EMI sources.