A step stress (10k, 20k, 30k and 50k) test method was used to determine the TID hardness level. That is, after a predetermined TID level was reached, an electrical test was performed on a given sample of parts to verify that the units are within specified data sheet electrical test limits. From initial feasibility studies the difference between pre- and post irradiation was greater for samples that were biased. For example, for RLAT 22 sample units were used at the 209-264 rad(Si)/s dose level with biased setup conditions and this is repeated for each wafer lot. The RLAT units were parametrically tested on ATE and then put through 25ºC anneal for 50 hours. The units were then put through parametric testing on the ATE and passed all tests to the specified SMD test limits.

Table 2-1 lists the serialized samples used for TID characterization.