SBOK079 October 2023 TPS7H2140-SEP
PRODUCTION DATA
The TPS7H2140-SEP is fabricated in the TI Linear BiCMOS 250-nm process with a back-end-of-line (BEOL) stack consisting of five levels of standard thickness aluminum metal on a 0.6-μm pitch. The total stack height from the surface of the passivation to the silicon surface is 5.46 μm based on nominal layer thickness as shown in Figure 5-1. Accounting for energy loss through the 1-mil thick Aramica beam port window, the 40-mm air gap, and the BEOL stack over the TPS7H2140-SEP, the effective LET (LETEFF) at the surface of the silicon substrate, the depth, and the ion range was determined with the SEUSS 2020 Software (provided by the Texas A&M Cyclotron Institute and based on the latest SRIM-2013 [7] models). Table 5-1 lists the results.
Ion Type | Angle of Incidence | Degrader Steps (Number) | Degrader Angle | Range in Silicon | LETEFF (MeV·cm2/ mg) |
---|---|---|---|---|---|
109Ag | 0 | 0 | 0 | 99.2 | 48 |