SBOU282A December 2022 – March 2023 OPA928
The T-switch consists of two MOSFET relays (K1, K2) and one 10-kΩ resistor (R5). To drive the relays, connect two individually controlled 5-V power-supply channels to J7. Figure 4-3 shows the timing diagram for driving K1 and K2 in a break-before-make configuration. From Figure 4-3, t1, t2, and t4 are based on the maximum on and off time of the relays. Follow this timing to prevent the input from being connected directly to ground, which drives the output into the rail. The discharge time (t3) varies and must be defined by the user.
When the pins of J7 are not actively driven, the control logic is pulled to ground by R11 and R12, resulting in a default logic low for normal TIA operation.
Figure 4-4 shows the simplified T-switch circuit in an integrator configuration during normal operation (logic low). The input current source shown is a reverse-biased photodiode. K2 is connected to the input of the integrator and is normally open. K1 is normally closed and connects K2 and R5 to ground. When the T-switch is not active, R5 is a 10-kΩ load to ground at the output of the amplifier. The Omron G3VM-81PR(TR05) MOS FET relay was chosen for K2 for the high insulation resistance and low open-switch capacitance. When K1 is closed and K2 is open, the potential across K2 is nearly 0 V, and the high insulation resistance limits any leakage current to negligible levels. Figure 4-5 shows the functionally equivalent circuit (ignoring switch nonidealities) when the T-switch is logic low.
When the T-switch is logic low, the integrating capacitor, CF, accumulates charge that appears as a ramping voltage at the amplifier output. The average current for any measurement period is calculated the following equation.
where
In the case of a unidirectional current source at the input, the integrating capacitor continues to accumulate charge until the amplifier output is driven into the rail and feedback is lost. To prevent the amplifier from railing, drive the T-switch high to discharge the capacitor and reset the measurement.
Figure 4-6 shows the simplified T-switch circuit when the logic is driven high and the feedback is discharged. K1 opens and K2 closes, switching 10-kΩ resistor R5 into the feedback parallel to CF. This 10-kΩ resistor provides a path for CF to discharge, and the output voltage settles to the level defined by Equation 2. The settling time depends on the output voltage and the RC time constant of the circuit.
where
Figure 4-7 shows the functionally equivalent circuit (ignoring switch nonidealities) when the T-switch is logic high. When K2 is closed and K1 is open, switch K1 presents 100 pF of capacitance at the input of the amplifier. An additional capacitor, C9, is populated in parallel to R5 to maintain stability when the T-switch is active.