1 Introduction

Paralleling LDO’s using ballast resistors have been discussed in the industry for many years. Traditionally, the analysis techniques that have been developed are limited to two parallel LDO’s, and ballast resistance calculations are limited to current imbalance of the LDOs. More recently Texas Instruments published a technical white paper to enable parallel designs of any number of LDOs while also meeting the load voltage [see reference 4]. A detailed discussion on key system specifications (such as temperature, PSRR, noise, and dropout voltage) is missing entirely from the literature.

Modern systems require parallel LDO designs to meet more than just additional load current and methods to accurately design with more than two parallel LDO’s must be developed. Many engineers want to use 5-10 parallel LDO’s to meet their system requirements such as noise, load voltage, temperature, dropout, and PSRR. We must be able to derive the minimum number of parallel LDO’s required to meet these system specifications based on a worst-case analysis. This technical white paper will provide a new mathematical foundation to answer these questions. From this, we can support a new generation of designs which may parallel any number of LDO’s required to meet the system noise, load voltage, load current, temperature, dropout, and PSRR specifications.