2 Latch-Up Testing Methods

Latch-Up stress methods prior to the late 1980’s were accomplished on bench set-ups with the use of curve tracers or other bench set-ups. In 1988, an industry team released the first Latch-Up standard, JESD17. This standard proposed a method of characterization based mostly on digital CMOS circuit concepts. In 1997, the JEDEC team proposed another Latch-Up standard (JESD78) that built on JESD17 adding more detail to the stress and giving a robustness criteria for the first time. JESD78 remains a standard mostly based on digital CMOS technology and test methods. The current revision, Revision D, does not have a robustness criterion; it has reverted to being a characterization standard. Analog products do not necessarily fit well into the methodology since there are generally specific bias values that work outside a zero or one condition. There are efforts underway on the JEDEC Latch-Up team to add analog methodology, which will likely be completed late in 2015.