SCDS418D July   2020  – September 2021

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Source or Drain Continuous Current
    6. 7.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 7.7  ±15 V Dual Supply: Switching Characteristics 
    8. 7.8  ±20 V Dual Supply: Electrical Characteristics
    9. 7.9  ±20 V Dual Supply: Switching Characteristics
    10. 7.10 44 V Single Supply: Electrical Characteristics 
    11. 7.11 44 V Single Supply: Switching Characteristics 
    12. 7.12 12 V Single Supply: Electrical Characteristics 
    13. 7.13 12 V Single Supply: Switching Characteristics 
    14. 7.14 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Off-Leakage Current
    3. 8.3  On-Leakage Current
    4. 8.4  Transition Time
    5. 8.5  tON(EN) and tOFF(EN)
    6. 8.6  Break-Before-Make
    7. 8.7  tON (VDD) Time
    8. 8.8  Propagation Delay
    9. 8.9  Charge Injection
    10. 8.10 Off Isolation
    11. 8.11 Crosstalk
    12. 8.12 Bandwidth
    13. 8.13 THD + Noise
    14. 8.14 Power Supply Rejection Ratio (PSRR)
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Rail-to-Rail Operation
      3. 9.3.3 1.8 V Logic Compatible Inputs
      4. 9.3.4 Integrated Pull-Down Resistor on Logic Pins
      5. 9.3.5 Fail-Safe Logic
      6. 9.3.6 Latch-Up Immune
      7. 9.3.7 Ultra-Low Charge Injection
    4. 9.4 Device Functional Modes
    5. 9.5 Truth Tables
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Detailed Design Procedure

The application shown in Figure 10-1 demonstrates demonstrates how a multiplexer can be used to simplify the signal chain and monitor multiple input signals to a single ADC channel. In this example the ADC (ADS8661) has software programmable input ranges up to ±12.288 V. The ADC also has overvoltage protection up to ±20 V which allows for the multiplexer to be powered with wider supply voltages than the input signal range to maximize on resistance performance of the multiplexer, while still maintaining system level overvoltage protection beyond the useable signal range. Both the multiplexer and the ADC are capable of operation in extended industrial temperature range of -40°C to +125°C allowing for use in a wider array of industrial systems.

Many SAR ADCs have an analog input structure that consists of a sampling switch and a sampling capacitor. Many signal chains will have a driver amplifier to help charge the input of the ADC to meet a fast system acquisition time. However a driver amplifier is not always needed to drive SAR ADCs. Figure 10-2 shows a typical diagram of a sensor driving the SAR ADC input directly after being passed through the multiplexer. A filter capacitor (CFLT) is connected to the input of the ADC to reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitor of the ADC.

The sensor block simplifies the device into a Thevenin equivalent voltage source (VTH) and resistance (RTH) which can be extracted from the device datasheets. Similarly the multiplexer can be thought of as a series resistance (RON(MUX)) and capacitance (CON(MUX)). To ensure maximum precision of the signal chain the system should be able to settle within 1/2 of an LSB within the acquisition time of the ADC. The time constant can be calculated as shown in Figure 10-2. This equation highlights the importance of selecting a multiplexer with low on-resistance to further reduce the system time constant. Additionally low charge injection performance of the multiplexer is helpful to reduce conversion errors and improve accuracy of the measurements.

GUID-20201110-CA0I-TV4V-JNHM-HWGLDLXLNNB0-low.gif Figure 10-2 Driving SAR ADC