SCDS445D May 2022 – September 2024
PRODUCTION DATA
Table 8-1, Table 8-2, and Table 8-3 provides the truth tables for the TMUX4051 respectively.
| EN | A2 | A1 | A0 | Selected Signal Path Connected To Drain (D) Pin |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | S0 |
| 0 | 0 | 0 | 1 | S1 |
| 0 | 0 | 1 | 0 | S2 |
| 0 | 0 | 1 | 1 | S3 |
| 0 | 1 | 0 | 0 | S4 |
| 0 | 1 | 0 | 1 | S5 |
| 0 | 1 | 1 | 0 | S6 |
| 0 | 1 | 1 | 1 | S7 |
| 1 | X(1) | X(1) | X(1) | All inputs are unselected (HI-Z) |
| EN | A1 | A0 | Selected Signal Path Connected To Drain (DA and DB) Pins |
|---|---|---|---|
| 0 | 0 | 0 | S0A to DA S0B to DB |
| 0 | 0 | 1 | S1A to DA S1B to DB |
| 0 | 1 | 0 | S2A to DA S2B to DB |
| 0 | 1 | 1 | S3A to DA S3B to DB |
| 1 | X(1) | X(1) | All inputs are unselected (HI-Z) |
| EN | SEL1 | SEL2 | SEL3 | Selected Signal Path Connected To Drain Pins |
|---|---|---|---|---|
| 0 | 0 | X | X | S1A to D1 |
| 0 | 1 | X | X | S1B to D1 |
| 0 | X | 0 | X | S2A to D2 |
| 0 | X | 1 | X | S2B to D2 |
| 0 | X | X | 0 | S3A to D3 |
| 0 | X | X | 1 | S3B to D3 |
| 1 | X(1) | X(1) | X(1) | All inputs are unselected (HI-Z) |
The Enable pin, EN, of the TMUX405x devices have a weak internal pull-up resistor to put the devices into a disabled state upon power up. The SELx / Address pins (Ax) have weak internal pull-down resistors to put the switch into a defined logic state.