1 Device Information

The SN54SC2T74-SEP contains two independent D-type positive-edge-triggered flip-flops. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2-V input to 1.8-V output or 1.8-V input to 3.3-V output.) Additionally, the 5-V tolerant input pins enable down translation (for example, 3.3-V to 2.5-V output). The SN54SC2T74-SEP is a pure CMOS device and therefore was tested at a High Dose Rate (HDR) for TID testing.