SCLK048 February 2024 SN54SC6T07-SEP
A step stress (10k, 20k, 30k and 50k) test method was used to determine the TID hardness level. That is, after a predetermined TID level was reached, an electrical test was performed on a given sample of parts to verify that the units are within specified data sheet electrical test limits. The RLAT units were parametrically tested on ATE and then put through 25ºC anneal for 72 hours. The units were then put through parametric testing again on the ATE.
Table 2-1 lists the serialized samples used for TID characterization.
| Control Group | HDR = 192.51rad(Si)/s | ||||
|---|---|---|---|---|---|
| Total Samples: 4 | Total Samples: 27 | ||||
| Exposure Levels | |||||
| 0krad (Si) | 10krad (Si) | 20krad(Si) | 30krad(Si) | 50krad (Si) | |
| Biased | Biased | Biased | Biased | Biased + 72 hour anneal | Biased |
| 1 - 4 | 5 - 9 | 10 - 14 | 15 - 20 | 21 - 26 | 27 - 31 |