PLL Lock functionality is implemented by comparing the difference(error) between the feedback clock and reference clock through Phase Frequency Detector (PFD). When PLL is in lock and generating the correct frequency, the difference(error) is <100pS~300pS. Once there is any fault causing the PLL output frequency to drift, the difference will go outside of that range. In such a case, PLL Lock signal will go from 1 to 0 indicating PLL is out of lock. The tolerance of PLL lock indication is configurable by software. SoC should use this signal as a critical interrupt/NMI to take the MCU into a safe state.