4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the DRV8705-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

• Pin short-circuited to Ground (see Table 4-2 for SPI variant, see Table 4-3 for HW variant)
• Pin open-circuited (see Table 4-4 for SPI variant, see Table 4-5 for HW variant)
• Pin short-circuited to an adjacent pin (see Table 4-6 for SPI variant, see Table 4-7 for HW variant)
• Pin short-circuited to supply (PVDD) (see Table 4-8 for SPI variant, see Table 4-9 for HW variant)

Table 4-2 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Figure 4-1 and Figure 4-2 show the DRV8705-Q1 pin diagrams. The DRV8705-Q1 has two pin diagram variants, an SPI variant (DRV8705S-Q1) and a HW variant (DRV8705H-Q1). For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the DRV8705-Q1 data sheet.

Figure 4-1 DRV8705S-Q1 Pin Diagram

Figure 4-2 DRV8705H-Q1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

• The device is used with external components consistent with the values described in the external component table and primary application section of the datasheet.