SFFS101 March 2021 TPS628501 , TPS628502
The failure mode distribution estimation for TPS62850x in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
SW no output | 35% |
SW output not in specification - voltage or timing | 45% |
SW power HS or LS FET stuck on | 10% |
PG false trip or fails to trip | 5% |
Short circuit any two pins | 5% |