SFFS167C September   2021  – September 2024 ADS117L11 , ADS127L11 , ADS127L21

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 TSSOP Package
    2. 2.2 WQFN Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 TSSOP Package
    2. 4.2 WQFN Package
  7. 5Revision History

WQFN Package

Figure 4-2 shows the ADS117L11, ADS127L11, ADS127L21, and ADS127L21B pin diagram for the WQFN package. For a detailed description of the device pins, see the Pin Configuration and Functions sections in the ADS117L11, ADS127L11, ADS127L21, and ADS127L21B data sheets.

ADS127L11 ADS117L11 ADS127L21 ADS12L7L21B Pin Diagram (WQFN Package) Figure 4-2 Pin Diagram (WQFN Package)
Table 4-6 RUK Package Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
AINP 1 AINP is stuck low. Conversion results are correct only if AINP is tied to DGND in actual use, otherwise conversion results are incorrect. B
AINN 2 AINN is stuck low. Conversion results are correct only if AINN is tied to DGND in actual use, otherwise conversions results are incorrect. B
VCM 3 VCM is stuck low. Conversion results are incorrect if actively used for the external driver stage to set the signal common-mode voltage. B
REFP 4 REFP is stuck low. Conversion results are incorrect. B
REFN 5 REFN is stuck low. Conversion data are correct only if REFN is tied to DGND in actual use, otherwise conversions results are incorrect. B
RESET 6 RESET is stuck low. The device is not functional. B
CS 7 CS is stuck low in four-wire SPI mode. SPI communication is not functional because of inability to control SPI data frames. B
CS is stuck low in three-wire SPI mode. No effect, conversions results are correct. D
SDI 8 SDI is stuck low. Loss of SPI input communications to the device. Conversion data readout remains functional. B
SCLK 9 SCLK is stuck low. SPI communication is not possible. B
SDO/DRDY 10 SDO/DRDY is stuck low. SPI output communication is not possible. SPI input communication remains functional. The data-ready function with this pin is not functional. Device damage plausible if SDO/DRDY is shorted to ground for an extended period of time. A
DRDY 11 DRDY is stuck low, this pin is not monitored by the host. Normal operation. Device damage is plausible if DRDY is shorted to ground for an extended period of time. A
DRDY is stuck low, this pin is monitored by the host. No data-ready indication with DRDY to the host is possible. Device damage is plausible if DRDY is shorted to ground for an extended period of time. A
CLK 12 CLK is stuck low in external clock mode. The device is not functional. Conversion results are incorrect. B
CLK is stuck low in internal clock mode. No effect. Normal operation. D
IOVDD 13 The device is not powered and not functional. B
DGND 14 No effect. Normal operation. D
CAPD 15 The device is partially not powered and not functional. Device damage is plausible if CAPD is shorted to ground for an extended period of time. A
START 16 START is stuck low, this pin is in active use by the host. Loss of ability to control conversion timing. Conversion results are incorrect. B
START is stuck low, this pin is tied low in actual use (software control mode). No effect. Normal operation. D
AVSS 17 No effect. Normal operation. D
CAPA 18 The device is partially not powered and is not functional. Device damage is plausible if CAPA is shorted to ground for an extended period of time. A
AVDD2 19 The device is not powered and not functional. B
AVDD1 20 The device is not powered and not functional. Observe that the absolute maximum ratings for the analog input and reference voltage pins of the device are met, otherwise device damage is plausible. A
Thermal pad –- No effect. Normal operation. D
Table 4-7 RUK Package Pin FMA for Device Pins Open-Circuited
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
AINP 1 State of AINP is indeterminate. Conversion results are indeterminate. B
AINN 2 State of AINN is indeterminate. Conversion results are indeterminate. B
VCM 3 VCM output voltage is indeterminate. Conversion results are indeterminate. B
REFP 4 State of REFP is indeterminate. Conversion results are indeterminate. B
REFN 5 State of REFN is indeterminate. Conversion results indeterminate. B
RESET 6 RESET is stuck high. Loss of ability to reset the ADC with this pin. B
CS 7 State of CS is indeterminate. SPI communication is corrupted. B
SDI 8 State of SDI is indeterminate. Loss of SPI input communication to the device. Conversion data readout remains functional. B
SCLK 9 State of SCLK is indeterminate. SPI communication is corrupted. B
SDO/DRDY 10 State of SDO/DRDY is indeterminate. SPI output communication is not possible. SPI input communication remains functional. Loss of data-ready function from this pin. B
DRDY 11 DRDY is unconnected, this pin is not monitored by the host. No effect. Normal operation. D
DRDY is unconnected, this pin is monitored by the host. No data-ready indication with DRDY to the host is possible. B
CLK 12 CLK is open circuit in external clock mode. The device is not functional. Conversion results are incorrect. B
CLK is open circuit in internal clock mode. No effect. Normal operation. D
IOVDD 13 Device functionality is undetermined. The device is partially not powered and not functional if the START digital input pin is held low. The device can be powered through the START digital input pin by an internal ESD diode conduction path to IOVDD. B
DGND 14 Device functionality is indeterminate. The device can be not powered, or powered through digital inputs by an ESD diode path. B
CAPD 15 CAPD voltage is indeterminate. Conversion results are indeterminate. B
START 16 State of START is indeterminate. Conversion results are indeterminate. B
AVSS 17 Device functionality is indeterminate. The device is not powered and not functional if the analog input or voltage reference pins are held low. The device can be powered through input or voltage reference drivers through an internal ESD diode conduction path. B
CAPA 18 CAPA voltage is indeterminate. Conversion results are indeterminate. B
AVDD2 19 The device is partially not powered and held in reset. The device is not functional. B
AVDD1 20 Device functionality is indeterminate. The device is partially not powered and not functional if the analog input or voltage reference pins are held low. The device can be powered through input or voltage reference drivers through an internal ESD diode conduction path. B
Thermal pad The device remains functional with possible performance degradation. C
Table 4-8 RUK Package Pin FMA for Device Pins Short-Circuited to Adjacent Pins
Pin Name Pin No. Shorted to Description of Potential Failure Effects Failure Effect Class
AINP 1 AINN Conversion results are incorrect. Conversion result is close to 0V. B
AINN 2 VCM Conversion results are incorrect. B
VCM 3 REFP Conversion results are incorrect. B
REFP 4 REFN Conversion results are incorrect. B
REFN 5 RESET Not considered. Corner pins. D
RESET 6 CS Conversion results are incorrect. The device is not functional. B
CS 7 SDI Loss of SPI input communication to the device if the driver source impedance of CS exceeds that of SDI. Loss of all SPI communication to the device if the driver source impedance of SDI exceeds that of CS. B
SDI 8 SCLK Loss of SPI input communication to the device if the driver source impedance of SCLK exceeds that of SDI. Loss of all SPI communication to the device if the driver source impedance of SDI exceeds that of SCLK. B
SCLK 9 SDO/DRDY Loss of SPI output communication from the device if the driver source impedance of SCLK exceeds that of SDO/DRDY. Loss of all SPI communication to the device if the driver source impedance of SDO/DRDY exceeds that of SCLK. Device damage is plausible if shorted together for an extended period of time. A
SDO/DRDY 10 DRDY Not considered. Corner pins. D
DRDY 11 CLK External clock mode. The device is not functional if the driver source impedance of DRDY exceeds that of CLK. Indeterminate state of DRDY if the driver source impedance of CLK exceeds that of DRDY. Device damage is plausible if shorted together for an extended period of time. A
Internal clock mode. The CLK pin has an external pullup or pulldown resistor to supply or ground (no active driver used). Normal operation. D
CLK 12 IOVDD External clock mode. The device is not functional. Conversion results are incorrect. B
Internal clock mode. Normal operation. D
IOVDD 13 DGND The device is partially not powered and not functional. B
DGND 14 CAPD The device is partially not powered and not functional. Device damage is plausible if CAPD is shorted to ground for an extended period of time. A
CAPD 15 START Not considered. Corner pins. D
START 16 AVSS Conversion results are correct only if START is tied to DGND = AVSS in actual use. Otherwise, conversion results are not correct because of the inability to control conversions. B
AVSS 17 CAPA The device is partially not powered and not functional. B
CAPA 18 AVDD2 CAPA is stuck high. Permanent device damage. A
AVDD2 19 AVDD1 No effect. Normal operation. D
AVDD1 20 AINP Not considered. Corner pins. D
Thermal pad All pins See the device pins short circuited to ground table (Table 4-6). -
Table 4-9 RUK Package Pin FMA for Device Pins Short-Circuited to Supply
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
AINP 1 AINP is stuck high. Conversion results are correct only if AINP is tied to AVDD1 in actual use, otherwise conversion results are incorrect. B
AINN 2 AINN is stuck high. Conversion results are correct only if AINN is tied to AVDD1 in actual use, otherwise conversion results are incorrect. B
VCM 3 VCM is stuck high. Conversion results are incorrect. B
REFP 4 REFP is stuck high. Conversion results correct only if REFP is tied to AVDD1 in actual use, otherwise conversions results incorrect. B
REFN 5 REFN is stuck high. Conversion results are incorrect. B
RESET 6 RESET is stuck high. Normal operation except for the loss of RESET functionality. B
CS 7 CS is stuck high. SPI communication is not functional. B
SDI 8 SDI is stuck high. Loss of SPI input communication to the device. Conversion data readout remains functional. B
SCLK 9 SCLK is stuck high. SPI communication is not possible. B
SDO/DRDY 10 SDO/DRDY is stuck high. SPI communication is not functional. Data ready is not functional. Device damage is plausible if SDO/DRDY is shorted to the supply for an extended period of time. A
DRDY 11 DRDY is stuck high, this pin is not monitored. Normal operation. Device damage is plausible if DRDY is shorted to the supply for an extended period of time. A
DRDY is stuck high, this pin is monitored. No data-ready indication by DRDY to the host is possible. Device damage is plausible if DRDY is shorted to the supply for an extended period of time. A
CLK 12 CLK is stuck high in external clock mode. The device is not functional. Conversion results are incorrect. B
CLK is stuck high in internal clock mode. No effect. Normal operation. D
IOVDD 13 No effect. Normal operation. D
DGND 14 The device is not powered and not functional. B
CAPD 15 CAPD is stuck high. Permanent device damage. A
START 16 START is stuck high. Conversion results are correct only if START is tied to 5V in actual use. Otherwise, conversion results are incorrect because of loss of ability to control conversions. B
AVSS 17 The device is not powered and not functional. B
CAPA 18 CAPA is stuck high. Permanent device damage. A
AVDD2 19 No effect. Normal operation. D
AVDD1 20 No effect. Normal operation. D
Thermal pad The device is not powered and not functional. B