SFFS167C September 2021 – September 2024 ADS117L11 , ADS127L11 , ADS127L21
4.1 TSSOP Package
Figure 4-1 shows the ADS127L11 pin diagram for the TSSOP package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the ADS127L11 data sheet.
Figure 4-1 TSSOP Package Pin Diagram Table 4-2 PW Package Pin FMA for Device
Pins Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| CAPA | 1 | The device is partially not powered and not functional. Device damage is plausible if CAPA is shorted to ground for an extended period of time. | A |
| AVDD2 | 2 | The device is not powered and not functional. | B |
| AVDD1 | 3 | The device is not powered and not functional. Observe that the absolute maximum ratings for the analog input and reference voltage pins of the device are met, otherwise device damage is plausible. | A |
| AINP | 4 | AINP is stuck low. Conversion results are correct only if AINP is tied to DGND in actual use, otherwise conversion results are incorrect. | B |
| AINN | 5 | AINN is stuck low. Conversion results are correct only if AINN is tied to DGND in actual use, otherwise conversions results are incorrect. | B |
| VCM | 6 | VCM is stuck low. Conversion results are incorrect if actively used for the external driver stage to set the signal common-mode voltage. | B |
| REFP | 7 | REFP is stuck low. Conversion results are incorrect. | B |
| REFN | 8 | REFN is stuck low. Conversion data are correct only if REFN is tied to DGND in actual use, otherwise conversion results are incorrect. | B |
| RESET | 9 | RESET is stuck low. The device is not functional. | B |
| CS | 10 | CS is stuck low in four-wire SPI mode. SPI communication is not functional because of the inability to control the SPI data frames. | B |
| CS is stuck low in three-wire SPI mode. No effect, conversion results are correct. | D | ||
| SDI | 11 | SDI is stuck low. Loss of SPI input communication to the device. Conversion data readout remains functional. | B |
| SCLK | 12 | SCLK is stuck low. SPI communication is not possible. | B |
| SDO/DRDY | 13 | SDO/DRDY is stuck low. SPI output communication is not possible. SPI input communication remains functional. The data-ready function with this pin is not functional. Device damage is plausible if SDO/DRDY is shorted to ground for an extended period of time. | A |
| DRDY | 14 | DRDY is stuck low, this pin is not monitored by the host. Normal operation. Device damage is plausible if DRDY is shorted to ground for an extended period of time. | A |
| DRDY is stuck low, this pin is monitored by the host. No data-ready indication with DRDY to the host is possible. Device damage is plausible if DRDY is shorted to ground an for extended period of time. | A | ||
| CLK | 15 | CLK is stuck low in external clock mode. The device is not functional. Conversion results are incorrect. | B |
| CLK is stuck low in internal clock mode. No effect. Normal operation. | D | ||
| IOVDD | 16 | The device is not powered and not functional. | B |
| DGND | 17 | No effect. Normal operation. | D |
| CAPD | 18 | The device is partially not powered and not functional. Device damage is plausible if CAPD is shorted to ground for an extended period of time. | A |
| START | 19 | START is stuck low, this pin is in active use by the host. Loss of ability to control conversion timing. Conversion results are incorrect. | B |
| START is stuck low, this pin is tied low in actual use (software control mode). No effect. Normal operation. | D | ||
| AVSS | 20 | No effect. Normal operation. | D |
Table 4-3 PW Package Pin FMA for Device
Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| CAPA | 1 | CAPA voltage is indeterminate. Conversion results are indeterminate. | B |
| AVDD2 | 2 | The device is partially not powered and held in reset. The device is not functional. | B |
| AVDD1 | 3 | Device functionality is indeterminate. The device is partially not powered and not functional if the analog input or voltage reference pins are held low. The device can be powered through input or voltage reference drivers through an internal ESD diode conduction path. | B |
| AINP | 4 | State of AINP is indeterminate. Conversion results are indeterminate. | B |
| AINN | 5 | State of AINN is indeterminate. Conversion results are indeterminate. | B |
| VCM | 6 | VCM output voltage is indeterminate. Conversion results are indeterminate. | B |
| REFP | 7 | State of REFP is indeterminate. Conversion results are indeterminate. | B |
| REFN | 8 | State of REFN is indeterminate. Conversion results are indeterminate. | B |
| RESET | 9 | RESET is stuck high. Loss of ability to reset the ADC with this pin. | B |
| CS | 10 | State of CS is indeterminate. SPI communication is corrupted. | B |
| SDI | 11 | State of SDI is indeterminate. Loss of SPI input communication to the device. Conversion data readout remains functional. | B |
| SCLK | 12 | State of SCLK is indeterminate. SPI communication is corrupted. | B |
| SDO/DRDY | 13 | State of SDO/DRDY is indeterminate. SPI output communication is not possible. SPI input communication remains functional. Loss of data-ready function from this pin. | B |
| DRDY | 14 | DRDY unconnected, this pin is not monitored by the host. No effect. Normal operation. | D |
| DRDY unconnected, this pin is monitored by the host. No data-ready indication with DRDY to the host is possible. | B | ||
| CLK | 15 | CLK open-circuit in external clock mode. The device is not functional. Conversion results are incorrect. | B |
| CLK open-circuit in internal clock mode. No effect. Normal operation. | D | ||
| IOVDD | 16 | Device functionality is indeterminate. The device is partially not powered and not functional if the START digital input pin is held low. The device can be powered through the START digital input pin with an internal ESD diode conduction path to IOVDD. | B |
| DGND | 17 | Device functionality is indeterminate. The device can be not powered, or powered through digital inputs with an ESD diode path. | B |
| CAPD | 18 | CAPD voltage is indeterminate. Conversion results are indeterminate. | B |
| START | 19 | State of START is indeterminate. Conversion results are indeterminate. | B |
| AVSS | 20 | Device functionality is indeterminate. The device is not powered and not functional if the analog input or voltage reference pins are held low. The device can be powered through the input or voltage reference drivers through an internal ESD diode conduction path. | B |
Table 4-4 PW Package Pin FMA for Device
Pins Short-Circuited to Adjacent Pins
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| CAPA | 1 | AVDD2 | Device damage. | A |
| AVDD2 | 2 | AVDD1 | No effect. Normal operation. | D |
| AVDD1 | 3 | AINP | Conversion results are correct only if AINP is tied to AVDD1 in actual use, otherwise conversion results are incorrect. | B |
| AINP | 4 | AINN | Conversion results are incorrect. Conversion result is close to 0V. | B |
| AINN | 5 | VCM | Conversion results are incorrect. | B |
| VCM | 6 | REFP | Conversion results are incorrect. | B |
| REFP | 7 | REFN | Conversion results are incorrect. | B |
| REFN | 8 | RESET | Conversion results are incorrect. The device is held in reset and is not functional if the driver source impedance of REFN exceeds that of RESET, thus driving RESET to a low threshold. Otherwise, conversion results are incorrect. | B |
| RESET | 9 | CS | Conversion results are incorrect. The device is not functional. | B |
| CS | 10 | SDI | Not considered. Corner pins. | D |
| SDI | 11 | SCLK | Loss of SPI input communication to the device if the driver source impedance of SCLK exceeds that of SDI. Loss of all SPI communication to the device if the driver source impedance of SDI exceeds that of SCLK. | B |
| SCLK | 12 | SDO/DRDY | Loss of SPI output communication from the device if the driver source impedance of SCLK exceeds that of SDO/DRDY. Loss of all SPI communication to the device if the driver source impedance of SDO/DRDY exceeds that of SCLK. Device damage is plausible if shorted together for an extended period of time. | A |
| SDO/DRDY | 13 | DRDY | Indeterminate state of both digital outputs. Loss of SPI output communication from the device. Device damage is plausible if shorted together for an extended period of time. | A |
| DRDY | 14 | CLK | External clock mode. The device is not functional if the driver source impedance of DRDY exceeds that of CLK. Indeterminate state of DRDY if the driver source impedance of CLK exceeds that of DRDY. Device damage is plausible if shorted together for an extended period of time. | A |
| Internal clock mode. The CLK pin has external pullup or pulldown resistor to supply or ground (no active driver used). Normal operation. | D | |||
| CLK | 15 | IOVDD | External clock mode. The device is not functional. Conversion results are incorrect. | B |
| Internal clock mode. Normal operation. | D | |||
| IOVDD | 16 | DGND | The device is not powered and not functional. | B |
| DGND | 17 | CAPD | The device is partially not powered and not functional. Device damage is plausible if CAPD is shorted to ground for an extended period of time. | A |
| CAPD | 18 | START | The device is not functional. Permanent device damage if the START driver source impedance exceeds that of CAPD, resulting in CAPD exceeding the maximum voltage rating. | A |
| START | 19 | AVSS | Conversion results are correct only if START is tied to DGND = AVSS in actual use. Otherwise, conversion results are not correct because of inability to control conversions. | B |
| AVSS | 20 | CAPA | Not considered. Corner pins. | D |
Table 4-5 PW Package Pin FMA for Device
Pins Short-Circuited to Supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| CAPA | 1 | CAPA is stuck high. Permanent device damage. | A |
| AVDD2 | 2 | No effect. Normal operation. | D |
| AVDD1 | 3 | No effect. Normal operation. | D |
| AINP | 4 | AINP is stuck high. Conversion results are correct only if AINP is tied to AVDD1 in actual use, otherwise conversion results are incorrect. | B |
| AINN | 5 | AINN is stuck high. Conversion results are correct only if AINN is tied to AVDD1 in actual use, otherwise conversion results are incorrect. | B |
| VCM | 6 | VCM is stuck high. Conversion results are incorrect. | B |
| REFP | 7 | REFP is stuck high. Conversion results are correct only if REFP is tied to AVDD1 in actual use, otherwise conversion results are incorrect. | B |
| REFN | 8 | REFN is stuck high. Conversion results are incorrect. | B |
| RESET | 9 | RESET is stuck high. Normal operation except for loss of RESET functionality. | B |
| CS | 10 | CS is stuck high. SPI communication not functional. | B |
| SDI | 11 | SDI is stuck high. Loss of SPI input communication to the device. Conversion data readout remains functional. | B |
| SCLK | 12 | SCLK is stuck high. SPI communication is not possible. | B |
| SDO/DRDY | 13 | SDO/DRDY is stuck high. SPI communication is not functional. Data ready not functional. Device damage is plausible if SDO/DRDY is shorted to the supply for an extended period of time. | A |
| DRDY | 14 | DRDY is stuck high, this pin is not monitored. Normal operation. Device damage is plausible if DRDY is shorted to the supply for an extended period of time. | A |
| DRDY is stuck high, this pin is monitored. No data-ready indication with DRDY to the host is possible. Device damage is plausible if DRDY is shorted to supply for an extended period of time. | A | ||
| CLK | 15 | CLK is stuck high in external clock mode. The device is not functional. Conversion results are incorrect. | B |
| CLK is stuck high in internal clock mode. No effect. Normal operation. | D | ||
| IOVDD | 16 | No effect. Normal operation. | D |
| DGND | 17 | The device is not powered and not functional. | B |
| CAPD | 18 | CAPD is stuck high. Permanent device damage. | A |
| START | 19 | START is stuck high. Conversion results are correct only if START is tied to IOVDD in actual use. Otherwise, conversion results are incorrect because of the loss of ability to control conversions. | B |
| AVSS | 20 | The device is not powered and not functional. | B |