SFFS199 September 2021 ADS131B02-Q1
The failure mode distribution estimation for the ADS131B02-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
|
Incorrect conversion result of individual ADC(1) (for example, the ADC output code at positive or negative full scale, at 0 V, undetermined or otherwise incorrect) |
25% |
| SPI communication error | 15% |
|
Register bit error leading to incorrect device configuration (Device behavior depends on which user or internal register bit is affected) |
15% |
| Gain error of individual ADC out of specification(1) | 10% |
| Offset error of individual ADC out of specification(1) | 5% |
| Noise of conversion result of individual ADC out of specification(1) | 5% |
| INL of individual ADC out of specification(1) | 5% |
|
Gain error, INL, or noise of conversion results of both ADCs out of specification resulting from common circuitry (common circuitry includes internal supplies, voltage reference, bias current generator, and clock) |
5% |
|
Oscillator fault leading to incorrect data rate (for example, oscillator frequency too high or low, oscillator output stuck at) |
5% |
| ADC output code bit stuck at | 5% |
| Device behavior undetermined | 5% |