Clock setup for the TMS320F280015x MCU device family includes selecting the appropriate clock source, configuring the PLL multiplier, waiting for the lock status and switching the clock to the PLL output once the internal lock status is set. The time required for the PLL lock sequence can be profiled using on-chip timer to detect faults in the PLL wrapper logic. Once the PLL is locked, the frequency of the output clock can be checked by using the following:

• Dual-Clock Comparator (DCC)
• External Clock Monitoring via XCLKOUT to ensure proper clock output
• Clock Integrity Check Using CPU Timer
• Clock Integrity Check Using HRPWM