SFFS243 august 2021 DRV8143-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) of the pins for each of the device variants of DRV8143-Q1 as listed below.
- SPI "P" variant in HVSSOP package
- HW variant in VQFN-HR package
- SPI "S" variant in VQFN-HR package
The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground
- Pin open-circuited
- Pin short-circuited to an adjacent pin
- Pin short-circuited to supply
The analysis also indicates how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
Figure 4-1 Using dual DRV814x-Q1 as a
Full Bridge configuration with low-side recirculation- Test conditions:
- VVM = 13.5 V, TAmbient = 25°C , SPI "P" variant: VVDD = 5 V
- SPI "S" and "P" variant:
- DRVOFF ( pins combined) and IN pins controlled by controller
- IPROPI (pins combined) monitored by controller, nFAULT (pins combined) monitoring optional
- Configurations:
SPI_IN unlocked with
- DRVOFF_SEL = 1'b0 (Pin and register control for redundant shutoff)
- IN_SEL for switching half bridge device = 1'b1 (Pin only control for PWM)
- IN_SEL for non-switching half bridge device = 1'b0 (Register only control)
- HW variant:
-
- nSLEEP, DRVOFF, EN/IN1, PH/IN2 pins controlled by controller
- nFAULT and IPROPI pins monitored by controller
- NC pin floating