SFFS383 September 2022 TPS7A52-Q1
The failure mode distribution estimation for the TPS7A52-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| VOUT high (following VIN) | 15 |
| VOUT not in specification (voltage or timing) | 60 |
| VOUT low (no output) | 15 |
| PG false trigger (fails to trigger) | 5 |
| Short circuit any two pins | 5 |