MSPM0 L-series MCUs (MSPM0Lxx) include a low-power high-performance SRAM memory with zero wait state access across the supported CPU frequency range of the device. SRAM memory can be used for storing volatile information such as the call stack, heap, global data, and code. The SRAM memory content is fully retained in run, sleep, stop, and standby operating modes and is lost in shutdown mode. A write protection mechanism is provided to allow the application to prevent unintended modifications to a portion of the SRAM memory. SRAM write protection is useful when placing executable code into SRAM to provide a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption.​

For more details, see the "Platform memory map" chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual.

The following tests can be applied as functional safety mechanisms for this module (to provide diagnostic coverage on a specific function):

• SYSMEM1
• SYSMEM2
• SYSMEM5