SFFS638 December 2023 TPS4800-Q1
The failure mode distribution estimation for TPS4800-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
Gate output stuck high | 10% |
Gate output stuck low | 45% |
Gate output functional, not in specification voltage or timing | 34% |
Short circuit protection fails to trip or false trip | 5% |
UVLO fails to trip or false trip | 1% |
| Pin to Pin short any two pins | 5% |