SFFS667 November 2023 LMR36500
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the LMR36500. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure
Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the LMR36500 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LMR36500 data sheet.
Figure 4-1 Pin DiagramTable 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| RT | 1 | Switching Frequency is 2.2 MHz | D |
| PGOOD | 2 | When not in use can be left grounded (PGOOD is not a valid signal, VOUT normal) | D |
| EN/UVLO | 3 | VOUT = 0 V (Enable is off, functionality is halted) | D |
| VIN | 4 | VOUT = 0 V | B |
| SW | 5 | Damage HSFET | A |
| BOOT | 6 | VOUT = 0 V, HS will not turn on | B |
| VCC | 7 | VOUT = 0 V | B |
| VOUT/FB | 8 | VOUT = 0 V | B |
| GND | 9 | VOUT normal | D |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| RT | 1 | Frequency will not be defined. | C |
| PGOOD | 2 | When not in use, can be left open (PGOOD is not a valid signal, VOUT normal) | D |
| EN/UVLO | 3 | Pin cannot be left floating | B |
| VIN | 4 | VOUT = 0 V | B |
| SW | 5 | VOUT = 0 V | B |
| BOOT | 6 | VOUT = 0, HS will not turn on | B |
| VCC | 7 | VCC output will be unstable, can increase above 5.5 V | A |
| VOUT/FB | 8 | VOUT will be abnormal. Do not float this pin. | C |
| GND | 9 | VOUT can be abnormal, as reference voltage is not fixed | B |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| RT | 1 | PGOOD | If PGOOD is high, and less than 5.5 V Fsw = 1 MHz; If PGOOD is low, Fsw = 2.2 MHz. RT pin will become damaged if PG exceeds 5.5 V. | A |
| PGOOD | 2 | EN/UVLO | If EN/UVLO > 20 V, it will damage devices connected to PGOOD pin. | A |
| EN/UVLO | 3 | VIN | VOUT normal (Enable is on, all other blocks will work) | D |
| VIN | 4 | SW | Damage LSFET | A |
| SW | 5 | BOOT | VOUT = 0 V, HS will not turn on, no Cboot | B |
| BOOT | 6 | VCC | Damage will occur, break VCC Pin | A |
| VCC | 7 | VOUT/FB | If VOUT/FB votlage is less than 5.5 V, then no damage will occur. | B |
| VOUT/BIAS or FB | 8 | GND | VOUT = 0 V | B |
| GND | 9 | RT or MODE | If RT pin is already low, then the part is functional. Otherwise abnormal behavior. No damage to part. | B |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to
supply
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| RT | 1 | If Vin > 5.5 V, damage will occur. If Vin < 5.5 V, refer to the data sheet. | A |
| PGOOD | 2 | If VIN > 20 V, damage will occur. | A |
| EN/UVLO | 3 | VOUT normal (Enable is on, all other blocks will work). | D |
| VIN | 4 | VOUT normal. | D |
| SW | 5 | Damage LSFET. | A |
| BOOT | 6 | Damage will occur, BOOT ESD clamp will be damaged. | A |
| VCC | 7 | If Vin > 5.5, damage will occur. | A |
| VOUT/FB | 8 | If VIN > 16 V, damage will occur. | A |
| GND | 9 | VOUT = 0 V | B |