It is possible to test the functionality of the SRAM ECC by injecting single bit and double bit errors in test mode and performing reads on locations with ECC errors, and checking for the error response.

Flash ECC logic can be checked with the help of ECC test field ECC_TEST_EN in the FECC_CTRL register. This technique causes an output comparison failure between the redundant ECC logic upon a flash read access. Error response, diagnostic testability, and any necessary software requirements are defined by the software implemented by the system integrator.

For additional details on implementing this diagnostic for SRAM and FLASH memory, see the Application Test Hooks for Error Detection and Correction and Mechanism to Check the Correctness of ECC Logic sections in the device-specific technical reference manual.