The C2000 MCU device family products are primarily synchronous logic devices and as such require clock signals for proper operation. The clock management logic includes clock sources, clock generation logic including clock multiplication by phase lock loops (PLLs), clock dividers, and clock distribution logic. The registers that are used to program the clock management logic are located in the system control module. The following tests can be applied as diagnostics for this module (to provide diagnostic coverage on a specific function):

• CLK1 - Missing Clock Detect (MCD)
• CLK5 - External Monitoring of Clock via XCLKOUT
• CLK17 - Dual Clock Comparator (DCC)
• CLK6 - Internal Watchdog (WD)
• CLK7 - External Watchdog
• CLK2 - Clock Integrity Check Using CPU Timer
• CLK3 - Clock Integrity Check Using HRPWM
• CLK8 - Periodic Software Read Back of Static Configuration Registers
• CLK9 - Software Read Back of Written Configuration
• CLK13 - PLL Lock Profiling Using On-Chip Timer
• CLK14 - Peripheral Clock Gating (PCLKCR)

The following tests can be applied as test-for-diagnostics on this module to meet Latent Fault Metric Requirements:

• CLK10 - Software Test of Watchdog (WD) Operation
• CLK12 - Software Test of Missing Clock Detect Functionality

• DCC is the recommended method of clock monitoring over the CPU Timer or HRPWM-based methods.
• TI recommends the use of an external watchdog over an internal watchdog for mitigating the risk due to common mode failure. TI also recommends the use of a program sequence, windowed, or question and answer watchdog as opposed to a single threshold watchdog due to the additional failure modes that can be detected by a more advanced watchdog.
• Driving a high-frequency clock output on the XCLKOUT pin may have EMI implications. The selected clock needs to be scaled suitably before sending out through IO.