Figure 6-5 gives an overview of the BISTs used to monitor and diagnose the video output blocks in the DLP4620S-Q1 chipset.

Figure 6-5 Video Output BISTs

• [SM_8] Frame Buffer Swap Watchdog: Checks that the frame buffers are switching roles each frame. Each frame, one buffer stores processed video, and the other buffer outputs data to the DMD. If the buffers don't switch each frame, the video will not update. The software of the DLPC231S-Q1 sets a timer for the buffer swap. When the buffer is successfully swapped, a signal from the frame buffer controller resets the timer. If the swap does not happen within the allocated time, the timer will expire. If the timer expires, the test fails. Upon failure, emergency shutdown will be executed and an error will be logged. This test is always active when an external video source or internal test pattern are being used. This test is not executed when a splash image is being displayed.
• [SM_9] DMD High Speed Interface Training: The DLPC231S-Q1 to DMD sub-LVDS interface can adjust the phase of each signal in order to optimize the position of the clock signal within the data eye. This process compensates for variation in manufacturing, system temperature, and drive voltage. This process is called training. This training process can also detect faults in the DLPC231S-Q1 to DMD connection. The DMD low speed interface is used to configure the DMD for training and to read back the results of the training. This training is performed at start-up and continuously during display mode. A total of 8 frames is required to test all data pairs in theDLP4620S-Q1 chipset during display mode. If the test fails at start-up the system will stay in Stand-By mode, and an error will be logged. If failure happens during display mode, an error is logged. During display mode, failures may be transient. However, persistent errors can indicate a broken connection or another critical issue.
• [SM_10] DMD Low Speed Interface Test: Checks the DMD low speed interface by continuously writing a dedicated register and reading back the value. Reads and writes happen simultaneously with DMD High Speed Training Cycles. The DMD Low Speed Interface Test takes four total training cycles. A value is written in cycle 0, read back in cycle 1, the 1-s complement value is written in cycle 2, and another read is performed in cycle 3. This test is always executed during display mode. Upon failure, an error is logged.
• [SM_11] DMD Memory Test: Checks the DMD CMOS memory by writing data and confirming read back data. The DLPC231S-Q1 commands the DMD into a testing mode and the DMD writes known values into the memory cells below its pixels. The DMD then reads back the state of each memory cell and drives a signal to the DLPC231S-Q1 to indicate pass or fail for each column of the DMD memory. A column will be reported as a fail if one or more memory cells in that column reads an incorrect value. If a failure is detected in more than one column, the test fails. This test can be configured to run at start-up, and it can be executed by command after the software is changed to Stand-by mode via host command. In case of test failure, software will not transition Display Mode even if it is commanded by the host. An error will also be logged.
• [SM_12] DMD Reset Instruction Watchdog: Checks that the DMD has accepted command to update mirror positions. A reset command from the DLPC231S-Q1 tells the DMD to update mirror positions. If this command is not executed, mirrors will remain in their current position. Upon successfully receiving a reset command the DMD returns an acknowledge message. If this is not received by the DLPC231S-Q1 within an acceptable time, this test fails. Upon failure, emergency shutdown will be executed and an error will be logged. This test is always active when an image is being displayed.
• [SM_13] DMD Clock Monitor: The DLPC231S-Q1 clock generation block contains monitoring to ensure that the clock frequency of the DMD high speed interface is within the specified range.