SFFS757 February   2024 DLP4620S-Q1 , DLPC231S-Q1

1.   1
2. 1Introduction
   1.     Trademarks
3. 2 DLP4620S-Q1 Chipset Functional Safety Capability
4. 3Development Process for Management of Systematic Faults
   1. 3.1 TI New-Product Development Process
   2. 3.2 TI Functional Safety Development Process
5. 4 DLP4620S-Q1 Chipset Overview
   1. 4.1 Targeted Applications
   2. 4.2 DLP4620S-Q1 Chipset Functional Safety Concept
      1. 4.2.1 Typical Hazards
      2. 4.2.2 Chipset Architecture
      3. 4.2.3 Built-In Self Tests
   3. 4.3 Functional Safety Constraints and Assumptions
6. 5Description of Hardware Component Parts
   1. 5.1 Description of System Level Built In Self Test (BISTs)
7. 6Management of Random Faults
   1. 6.1 Fault Reporting
      1. 6.1.1 HOST_IRQ
      2. 6.1.2 Error History
      3. 6.1.3 Fault Handling
   2. 6.2 Functional Safety Mechanism Categories
   3. 6.3 Description of Functional Safety Mechanisms
      1. 6.3.1 Video Path Protection
         1. 6.3.1.1 Video Input BISTs
         2. 6.3.1.2 Video Processing BISTs
         3. 6.3.1.3 Video Output BISTs
      2. 6.3.2 Illumination Control Protection
         1. 6.3.2.1 Communication Interface and Register Protection
         2. 6.3.2.2 LED Control Feedback Loop Protection
         3. 6.3.2.3 Data Load and Transfer Protection
         4. 6.3.2.4 Watchdogs and Clock Monitors
         5. 6.3.2.5 Voltage Monitors
8.   A Summary of Recommended Functional Safety Mechanism Usage
9.   B Distributed Developments
   1.     B.1 How the Functional Safety Lifecycle Applies to TI Functional Safety Products
   2.     B.2 Activities Performed by Texas Instruments
   3.     B.3 Information Provided
10.   C Revision History