SFFS757 February   2024 DLP4620S-Q1 , DLPC231S-Q1

 

  1.   1
  2. 1Introduction
    1.     Trademarks
  3. 2 DLP4620S-Q1 Chipset Functional Safety Capability
  4. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
    2. 3.2 TI Functional Safety Development Process
  5. 4 DLP4620S-Q1 Chipset Overview
    1. 4.1 Targeted Applications
    2. 4.2 DLP4620S-Q1 Chipset Functional Safety Concept
      1. 4.2.1 Typical Hazards
      2. 4.2.2 Chipset Architecture
      3. 4.2.3 Built-In Self Tests
    3. 4.3 Functional Safety Constraints and Assumptions
  6. 5Description of Hardware Component Parts
    1. 5.1 Description of System Level Built In Self Test (BISTs)
  7. 6Management of Random Faults
    1. 6.1 Fault Reporting
      1. 6.1.1 HOST_IRQ
      2. 6.1.2 Error History
      3. 6.1.3 Fault Handling
    2. 6.2 Functional Safety Mechanism Categories
    3. 6.3 Description of Functional Safety Mechanisms
      1. 6.3.1 Video Path Protection
        1. 6.3.1.1 Video Input BISTs
        2. 6.3.1.2 Video Processing BISTs
        3. 6.3.1.3 Video Output BISTs
      2. 6.3.2 Illumination Control Protection
        1. 6.3.2.1 Communication Interface and Register Protection
        2. 6.3.2.2 LED Control Feedback Loop Protection
        3. 6.3.2.3 Data Load and Transfer Protection
        4. 6.3.2.4 Watchdogs and Clock Monitors
        5. 6.3.2.5 Voltage Monitors
  8.   A Summary of Recommended Functional Safety Mechanism Usage
  9.   B Distributed Developments
    1.     B.1 How the Functional Safety Lifecycle Applies to TI Functional Safety Products
    2.     B.2 Activities Performed by Texas Instruments
    3.     B.3 Information Provided
  10.   C Revision History

6.3.2.3 Data Load and Transfer Protection

The DLPC231S-Q1 contains several internal memories, such as the internal RAM and the sequencer memory. Data loaded into these memories comes from the external flash. The Flash Direct Memory Access (FDMA) block is used to facilitate the access and transport of data to the proper memories. To prevent or detect corruption of this data, the following features are implemented in the DLPC231S-Q1:

  • [SM_23] Flash Table Transport CRC: The DLPC231S-Q1 performs two CRC checks on all data that is transported from flash to internal memories such as IRAM and sequencer memory. When the data is originally generated, a CRC is calculated and appended to each block. When data is loaded from flash to an internal memory, the embedded software reads the expected CRC value from flash. Next, the FDMA block calculates a CRC as the data is transferred. This CRC is compared to the expected CRC. Lastly, another CRC is calculated by the destination memory (IRAM, sequencer memory, etc.) hardware. If the CRCs do not match at any point, the data will be re-loaded and an error will be logged.
  • [SM_24] ECC: The internal memories of the DLPC231S-Q1 implement ECC. The ECC can correct single-bit errors and detect, but not correct, multi-bit errors. In case of any errors, an error will be logged. In case of multi-bit errors an emergency shutdown will be executed.
  • [SM_25] DLPC231S-Q1 Memory BIST: Checks functionality of internal memories such as the frame buffers, internal RAM, and sequence look up tables using a series of writes, delays, and reads. The frame buffer memory check is critical for diagnosing a corrupt video path. The SRAM frame buffers are tested using a series of instructions provided by the manufacturer of the SRAM cell. The instructions for executing the test are stored in external flash, but the test data is generated locally in the frame buffer. If the data read from the memory does not match the data written to the memory the test fails. This test can be configured to run at start-up, and it can be executed by command after the software is changed to Stand-by mode using the host command. In case of test failure, software will not transition Display Mode even if it is commanded by the host. An error will also be logged.
  • [SM_26] Flash Data Verification: Each block of flash data contains an expected CRC. The DLPC231S-Q1 software calculates the CRC of each block and compares it to the expected CRC stored in flash. If there is a mismatch, the test fails. This test is typically executed after programming flash data. A flash option determines if this test is executed at start-up. TI recommends enabling this option. This test can also be executed from standby mode. In case of failure, software will not transition Display Mode even if it is commanded by the host. An error will also be logged.
  • [SM_27] Periodic Refresh: Memories in the DLPC231S-Q1 video path are periodically refreshed. For example, the frame buffers are reloaded every frame. The short reload period of these refreshes compared to the fault tolerant time interval means that the periodic refresh can be considered as a safety mechanism against transient errors in memories. Periodic refresh does not protect against permanent faults.
  • [SM_28] Boot ROM CRC: The boot application runs a CRC on the boot ROM data and compares it to an expected value stored in the boot ROM memory. If the CRCs do not match, the test fails. Upon failure, the failure stays in the boot application and does not proceed and logs an error.
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