SFFS961 August 2024 LMR51425-Q1 , LMR51435-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a failure mode analysis (FMA) for the pins of the LMR51425-Q1 and LMR51435-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Application circuit, as per the LMR51425-Q1 and LMR51435-Q1 data sheet is used.
Figure 4-1 shows the LMR51425-Q1 and LMR51435-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LMR51425-Q1 and LMR51435-Q1 data sheet.
Figure 4-1 Pin DiagramTable 4-2 Pin FMA for Device Pins Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| SW | 1 | Damage to internal power FETs and other internal circuits. | A |
| SW | 2 | Damage to internal power FETs and other internal circuits. | A |
| SW | 3 | Damage to internal power FETs and other internal circuits. | A |
| BOOT | 4 | VOUT = 0V, damage to internal circuits is possible. | A |
| PG | 5 | Power function is poor. | B |
| RT | 6 | Normal operation. | D |
| FB | 7 | The regulator operates at maximum duty cycle. Output voltage rises to nearly the input voltage (VIN) level. Damage to customer load and output stage components is possible. No effect on device. | B |
| AGND | 8 | Normal operation. | D |
| EN | 9 | Loss of ENABLE functionality. Device remains in shutdown mode. | B |
| VIN | 10 | Device does not operate. No output voltage is generated. Output capacitors discharge through the input short. A large current reversal can damage the device. | A |
| VIN | 11 | Device does not operate. No output voltage is generated. Output capacitors discharge through the input short. A large current reversal can damage the device. | A |
| VIN | 12 | Device does not operate. No output voltage is generated. Output capacitors discharge through the input short. A large current reversal can damage the device. | A |
| PGND/DAP | 13 | Normal operation. | D |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| SW | 1 | Loss of output voltage with both pins open. Reduced device performance with one pin open. | B |
| SW | 2 | Loss of output voltage with both pins open. Reduced device performance with one pin open. | B |
| SW | 3 | Loss of output voltage with both pins open. Reduced device performance with one pin open. | B |
| BOOT | 4 | Loss of output voltage regulation; low or no output voltage. | B |
| PG | 5 | Power function is poor. | B |
| RT | 6 | Normal operation. | D |
| FB | 7 | Loss of output voltage regulation. Output voltage can rise or fall outside of the intended regulation window. | B |
| AGND | 8 | Loss of output voltage regulation. Damage to internal circuits is possible. | A |
| EN | 9 | Loss of ENABLE functionality. Erratic operation; loss of regulation is probable. | B |
VIN | 10 | Loss of output voltage with both pins open. Device damage is possible with one pin open. | A |
| VIN | 11 | Loss of output voltage with both pins open. Device damage is possible with one pin open. | A |
| VIN | 12 | Loss of output voltage with both pins open. Device damage is possible with one pin open. | A |
| PGND/DAP | 13 | Loss of output voltage regulation. Damage to internal circuits is possible. | A |
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| SW | 1 | SW | No effect. | D |
| SW | 2 | SW | No effect. | D |
| SW | 3 | BOOT | VOUT = 0V, damage to internal circuits is possible. | A |
| BOOT | 4 | PG | PG pin ESD damage if BOOT pin voltage > 20V. | A |
| PG | 5 | RT | RT pin ESD damage if PG pin voltage > 5.5V. | A |
| FB | 7 | AGND | The regulator operates at maximum duty cycle. Output voltage rises to nearly the input voltage (VIN) level. Damage to customer load and output stage components is possible. No effect on device. | B |
| AGND | 8 | EN | Loss of ENABLE functionality. Device remains in shutdown mode. | B |
| EN | 9 | VIN | Normal operation, no damage to device. Loss of ENABLE functionality. | B |
| VIN | 10 | VIN | No effect. | D |
| VIN | 11 | VIN | No effect. | D |
| PGND/DAP | 13 | Any | Other pin is shorted to ground, see Table 4-2. | Any |
Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| SW | 1 | Damage to internal power FETs and other internal circuits. | A |
| SW | 2 | Damage to internal power FETs and other internal circuits. | A |
| SW | 3 | Damage to internal power FETs and other internal circuits. | A |
| BOOT | 4 | VOUT = 0V. BOOT ESD clamp runs current to destruction. | A |
| PG | 5 | Pin ESD Damage if supply voltage > 20V. | A |
| RT | 6 | Pin ESD Damage if supply voltage > 5.5V. | A |
| FB | 7 | If supply voltage exceeds 5.5V, damage occurs. VOUT = 0V. | A |
| AGND | 8 | Damage to internal circuits or package is possible. | A |
| EN | 9 | No damage to device. Loss of ENABLE functionality. | B |
| VIN | 10 | No effect. | D |
| VIN | 11 | No effect. | D |
| VIN | 12 | No effect. | D |
| PGND/DAP | 13 | Damage to internal circuits or package is possible. | A |