SFFSA14 October 2024 TPSI31P1-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a failure mode analysis (FMA) for the pins of the TPSI31P1-Q1 device. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to VSSP or VSSS (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to VDDP (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-2.
Table 4-1 TI Classification of Failure
Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the TPSI31P1-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the data sheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Device operated in standalone during normal operation, prior to any open or short condition being applied to the respective pin
- EN set to a static logic low or high (VDRV asserted low or high respectively)
- CE set to a static logic low or high.
- Opens or shorts occur relative to primary and secondary sides of the device and is a static event
Table 4-2 Pin FMA for Device Pins
Short-Circuited to VSSP or VSSS
| Pin Name | Pin No. | Ground | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| EN | 1 | VSSP | VDRV asserted low. | B |
| CE | 2 | VSSP | Device in standby. No power transfer. VDDH and VDDM rails discharge. VDRV is asserted low with keep-off circuitry enabled. | B |
| VDDP | 4 | VSSP | No power transfer. VDDH and VDDM rails collapse. VDRV is asserted low with keep-off circuitry enabled. | B |
| PGOOD | 5 | VSSP | PGOOD is asserted low. If PGOOD is not used, tie to VSSP. | B |
| NC | 6 | VSSP | No effect. | D |
| NC | 7 | VSSP | No effect. | D |
| IS+ | 11 | VSSS | If CE = H and EN = H, VDRV is asserted high. | B |
| IS+ | 12 | VSSS | If CE = H and EN = H, VDRV is asserted high. | B |
| VDDM | 13 | VSSS | VDDH and VDDM rails collapse. VDRV is asserted low with keep-off circuitry enabled. | B |
| VDDH | 15 | VSSS | VDDH and VDDM rails collapse. VDRV is asserted low with keep-off circuitry enabled. | B |
| VDRV | 16 | VSSS | If VDRV was high, VDDH and VDDM rails collapse. VDRV asserts low with keep-off circuitry enabled. If VDRV was low, no effect. | B |
Table 4-3 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| EN | 1 | VDRV asserted low. EN pin has an internal resistive pull-down to VSSP. | B |
| CE | 2 | Device powers off. VDDH and VDDM rails discharge. VDRV is asserted low with keep-off circuitry enabled. CE pin has an internal resistive pull-down to VSSP. | B |
| VSSP | 3 | Device has additional ground path through pin 8 (VSSP). | C |
| VDDP | 4 | No power transfer. VDDH and VDDM rails collapse. VDRV asserted low with active clamp enabled. | B |
| PGOOD | 5 | If PGOOD is unused, no effect. If PGOOD is used, and an external pull-up resistor is present, PGOOD asserted high is indicated to the system, regardless of actual status. | B |
| NC | 6 | No effect. | B |
| NC | 7 | No effect. | B |
| VSSP | 8 | Device has additional ground path through pin 3 (VSSP). | C |
| VSSS | 9 | Device has ground path through pin 14 (VSSS). Normal power transfer. VDDH and VDDM rails remain charged. VDRV follows state of EN logic level. | C |
| VSSS | 10 | Device has ground path through pins 9 and 14 (VSSS). Normal power transfer. VDDH and VDDM rails remain charged. VDRV follows state of EN logic level. | B |
| IS+ | 11 | IS+ pin has a weak internal resistive pull-down to VSSS and can be susceptible to switching noise. VDRV asserts high. | B |
| IS+ | 12 | IS+ pin has a weak internal resistive pull-down to VSSS and can be susceptible to switching noise. VDRV asserts high. | B |
| VDDM | 13 | VDDH and VDDM can collapse under loading or switching events. | B |
| VSSS | 14 | Device has ground path through pin 9 (VSSS). Normal power transfer. VDDH and VDDM rails remain charged. VDRV follows state of EN logic level. | C |
| VDDH | 15 | VDDH can collapse under loading or switching events. | B |
| VDRV | 16 | No drive to external switch. External switch gate control can float depending upon application circuitry. | B |
Table 4-4 Pin FMA for Device Pins Short-Circuited to
Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| VDRV | 16 | VDDH | If VDRV was low, VDDH and VDDM rails collapse. VDRV remains low with active clamp enabled. If VDRV was high, no effect. | B |
| IS+ | 12 | VDDM | IS+ comparator threshold can be reached causing VDRV to be asserted low. | B |
| IS+ | 12 | IS+ | Normal operation. | D |
| EN | 1 | CE | EN can be tied to CE in the application, if desired. | D |
| PGOOD | 5 | NC | NC output pin can drive low causing an electrical ORing of PGOOD with an open-drain output. PGOOD can be asserted low. | B |
| NC | 6 | NC | No effect. | D |
Table 4-5 Pin FMA for Device Pins Short-Circuited to
VDDP
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| EN | 1 | EN can be tied to VDDP in the application, if desired. | D |
| CE | 2 | CE can be tied to VDDP in the application, if desired. Device powers up depending on voltage level of VDDP. | D |
| PGOOD | 5 | Potential high current from VDDP while PGOOD is asserted low. Device can thermal cycle or be damaged. | A |
| NC | 6 | Potential high current from VDDP while NC open drain is asserted low. Device can thermal cycle or be damaged. | A |
| NC | 7 | Potential high current from VDDP while NC open drain is asserted low. Device can thermal cycle or be damaged. | A |