SLAA457B September 2013 – October 2018 MSP430F5500 , MSP430F5501 , MSP430F5502 , MSP430F5503 , MSP430F5504 , MSP430F5505 , MSP430F5506 , MSP430F5507 , MSP430F5508 , MSP430F5509 , MSP430F5510 , MSP430F5513 , MSP430F5514 , MSP430F5515 , MSP430F5517 , MSP430F5519 , MSP430F5521 , MSP430F5522 , MSP430F5524 , MSP430F5525 , MSP430F5526 , MSP430F5527 , MSP430F5528 , MSP430F5529 , MSP430F5630 , MSP430F5631 , MSP430F5632 , MSP430F5633 , MSP430F5634 , MSP430F5635 , MSP430F5636 , MSP430F5637 , MSP430F5638 , MSP430F5658 , MSP430F5659 , MSP430F6630 , MSP430F6631 , MSP430F6632 , MSP430F6633 , MSP430F6634 , MSP430F6635 , MSP430F6636 , MSP430F6637 , MSP430F6638 , MSP430F6658 , MSP430F6659 , MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626
The biggest consideration is precision. The USB specification requires the clock have a tolerance of ±2500 ppm. Sources that do not meet this may actually work under some conditions, perhaps with compromised performance. But choosing a source that meets the requirement will provide consistent best performance and ensure USB compliance.
With this in mind, the engineer has three basic choices to source the PLL reference, shown in Table 4.
| Source | Frequency Range | When to Use? |
|---|---|---|
| External clock source (put XT2 in "bypass" mode) | 1.5 to 32 MHz | If a clock that is always available during USB communication is present on the board, this is often the best choice, because it saves the cost of a crystal. However, if the USB BSL will be used, it must be modified for bypass mode, and this might affect its use for programming at production – see Section 3.6. |
| Crystal | 4 to 32 MHz | Crystals provide great flexibility and excellent precision. |
| Ceramic resonator | 4 to 32 MHz | Many resonators do not achieve the required tolerance. However, a few (for example, some parts within the Murata CERALOCK® family) do. These might be less expensive than crystals. |
NOTE
Always verify parameters against the most recent device data sheet.
See the Unified Clock System (UCS) chapter of the MSP430F5xx and MSP430F6xx Family User's Guide for information on sourcing a clock into the XT2 XIN pin in bypass mode.
The source must also not contain excessive jitter that would interfere with the PLL's ability to lock to it. (For this reason, the MSP430 FLL output cannot be used as a reference for the PLL.) Whether using a crystal or bypass mode, be sure the frequency is compatible with the options available for the programmable PLL (see the MSP430F5xx and MSP430F6xx Family User's Guide.
If using a crystal, the load capacitors should be properly chosen, according to the crystal's specification. This is especially true if the oscillator will be shut down during USB suspend to save power consumption, in which case improper capacitor selection could result in a slow response to USB resume. Improper capacitor values could cause crystal startup to take longer than it should, and the device has a total of 10 ms to become USB-ready when the host performs a USB resume on the device. If the oscillator had been disabled during suspend for power savings, then its re-enabling is part of this 10-ms budget. (A properly-tuned oscillator will easily meet the requirements.)
XT2 derives its power from the DVCC pin, rather from the internal USB LDO. Also, XT2 consumes approximately 200 to 400 µA, depending on the frequency (see the device data sheet for actual values).