SLAA517F May 2012 – August 2021 MSP430F6720A , MSP430F6720A , MSP430F6721A , MSP430F6721A , MSP430F6723A , MSP430F6723A , MSP430F6724A , MSP430F6724A , MSP430F6725A , MSP430F6725A , MSP430F6726A , MSP430F6726A , MSP430F6730A , MSP430F6730A , MSP430F6731A , MSP430F6731A , MSP430F6733A , MSP430F6733A , MSP430F6734A , MSP430F6734A , MSP430F6735A , MSP430F6735A , MSP430F6736 , MSP430F6736 , MSP430F6736A , MSP430F6736A
The MSP430F673x(A) family has up to three independent sigma delta data converters. For a single phase system at least two ΣΔs are necessary to independently measure one voltage and current. The code accompanying this application report addresses the metrology for a 1-phase system with limited discussion to anti-tampering, however, the code supports the measurement of the neutral current. The clock to the SD24 (fM ) is derived from the DCO running at 16 MHz. The sampling frequency is defined as , the OSR is chosen to be 256 and the modulation frequency, fM, is chosen as 1 MHz (1 048 576 Hz), resulting in a sampling frequency of 4.096 ksps. The SD24s are configured to generate regular interrupts every sampling instant.
The following are the ΣΔ channels associations: