7.3.1 ADC12 to ADC12_B

Some of the significant differences between the ADC12 and the ADC12_B module are:

• The ADC12_B is significantly lower power than the ADC12. To compare parameters such as supply current or reference buffer current, see the device-specific data sheet.
• The ADC12_B can operate across the entire voltage range of the device (1.8 V to 3.6 V).
• The ADC12_B module supports 16 single-ended external input channels. These can be combined to form 8 external differential input channels
• The ADC12_B provides a new feature called the Window Comparator that allows you to set threshold levels and compare conversion results to the thresholds. The thresholds are set in LSB units and, if a conversion result falls within the range of preset low and high threshold levels, an interrupt is triggered. Interrupts are also provided for when conversion results fall above or below the preset threshold levels. The same window comparator thresholds are shared among all channels, and conversion results from different channels are compared against the same threshold levels when the feature is enabled. This feature is extremely useful for saving power, because it allows the device to stay in LPM until the ADC input reaches a specific threshold. All other conversion results are discarded automatically, and the device only wakes up on threshold triggers.
• The ADC12 requires 13 ADC12CLKs for sample conversion. In contrast, the ADC12_B requires 10, 12, or 14 ADC12CLKs for sample conversion at 8-bit, 10-bit, or 12-bit resolutions, respectively.
• The formula for calculating the minimum sample time as highlighted in the section Sample Timing Considerations has changed. For details, see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide.
• The ADC12_B has 32 ADC12MEMCTLx (memory control) registers for sequenced channel operation and 32 dedicated interrupts for reading the conversion memory.
• The ADC12_B provides an option to enable 8-bit, 10-bit, or 12-bit conversion based on the ADC12RES bit in the ADC12_B Control 2 Register (ADC12CTL2).
• The ADC12_B provides the option to read data in 2s-complement format by setting the ADC12DF bit in the ADC12CTL2 register.
• An option to save power can be enabled at sampling frequencies less than 50 ksps using the ADC12PWRMD bit in the ADC12CTL2 register.
• For all parametric comparisons such as linearity, offset, total unadjusted error, and timing, see the device-specific data sheets. For all functional specifications on the ADC12_B, see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide.
• ADC12IE and ADC12IFG registers in the F2xx family have been replaced by ADC12_B Interrupt Enable 0 Register (ADC12IER0), ADC12_B Interrupt Enable 1 Register (ADC12IER1), ADC12_B Interrupt Flag 0 Register (ADC12IFG0), and ADC12IFG1 registers in the FR59xx family. To compare the register changes between the modules, see the device-specific user's guides.