6.1 Power Management Module (PMM)

The F2xx family of devices use a single voltage rail to power the chip; that is, a single power rail supplies both the analog peripherals and the digital core on the chip. The FR59xx family uses a split voltage supply. The external voltage supply on the DVCC pin is fed to an internal low-dropout voltage regulator (LDO) that supplies the CPU, memories, and digital modules, while AVCC supplies the analog modules (see Figure 1).

The PMM manages all functions related to the core voltage and its supervision. Its primary functions are, first, to generate a supply voltage for the core logic and, second, to provide several mechanisms for the supervision of both the voltage supplied to the device (DV_CC) and the voltage generated for the core (V_CORE).

Figure 1. PMM Block Diagram

Using a split supply is especially advantageous as it allows the core to operate at a lower voltage, which brings significant power savings. It also ensures that the core receives a stable and regulated voltage over a wide supply range.

This allows the FR59xx devices to operate across the entire voltage range of the device at the maximum device frequency of 16 MHz. In comparison, F2xx devices have a relationship between system frequency and supply voltage that must be adhered to in order to ensure proper operation of the device.

Because supply voltage supervision is an important aspect of providing a stable supply or a notification in case of power failure, the FR59xx provides an high-side supply voltage supervision (SVSH) block. The SVSH handles the supervision of the external chip supply (DV_CC), the low-side supervision of the core is handled internally by the PMM.

The SVS threshold tracks directly with the device minimum supply of 1.8 V, and there is no need to program SVS high-side levels as in the F2xx family (in which the SVS feature is available on select devices only). Also, the SVSH block in the FR59xx is highly simplified. It is on by default at power-up and stays on in active, LPM0, LPM1, and LPM2 modes. It can be turned off in LPM3, LPM4, and LPMx.5 modes, if required.

A useful feature in the FR59xx family is the ability to trigger an NMI when the supply falls below the SVS level. This is useful, for example, if a battery-powered application is low on charge. In this case, an interrupt can be used to configure ports to consume the least power and set the device in LPM3.5, consuming approximately 500 nA to maximize battery life while preserving RTC for as long as possible. The interrupt can also be used to warn the end user about the low battery state and to power down gracefully.

One of the main differences between the two families that can be observed while debugging can be attributed to the PMM module. In the FR59xx family, the V_COREregulator operates in two modes to conserve power: high-performance mode (used in active, LPM0, and LPM1 modes) and low-power mode (used in LPM2, LPM3, and LPM4 modes). When the FR59xx device is plugged into the debugger, it automatically forces the LDO to the high-performance mode regardless of the operating mode (active or LPM) that is set by the application code. In an application, this affects current consumption and wake-up times, which may cause the device to behave differently between stand-alone and debugger modes. When debugging with any of the lower LPMs (LPM2, LPM3, and LPM4), ensure that the debugger is disconnected to observe device performance accurately.