SLAA666A March 2015 – January 2020 MSP430F6720 , MSP430F6720A , MSP430F6721 , MSP430F6721A , MSP430F6723 , MSP430F6723A , MSP430F6724 , MSP430F6724A , MSP430F6725 , MSP430F6725A , MSP430F6726 , MSP430F6726A , MSP430F6730 , MSP430F6730A , MSP430F6731 , MSP430F6731A , MSP430F6733 , MSP430F6733A , MSP430F6734 , MSP430F6734A , MSP430F6735 , MSP430F6735A , MSP430F6736 , MSP430F6736A , MSP430F6745 , MSP430F67451 , MSP430F67451A , MSP430F6745A , MSP430F6746 , MSP430F67461 , MSP430F67461A , MSP430F6746A , MSP430F6747 , MSP430F67471 , MSP430F67471A , MSP430F6747A , MSP430F6748 , MSP430F67481 , MSP430F67481A , MSP430F6748A , MSP430F6749 , MSP430F67491 , MSP430F67491A , MSP430F6749A , MSP430F6765 , MSP430F67651 , MSP430F67651A , MSP430F6765A , MSP430F6766 , MSP430F67661 , MSP430F67661A , MSP430F6766A , MSP430F6767 , MSP430F67671 , MSP430F67671A , MSP430F6767A , MSP430F6768 , MSP430F67681 , MSP430F67681A , MSP430F6768A , MSP430F6769 , MSP430F67691 , MSP430F67691A , MSP430F6769A , MSP430F6775 , MSP430F67751 , MSP430F67751A , MSP430F6775A , MSP430F6776 , MSP430F67761 , MSP430F67761A , MSP430F6776A , MSP430F6777 , MSP430F67771 , MSP430F67771A , MSP430F6777A , MSP430F6778 , MSP430F67781 , MSP430F67781A , MSP430F6778A , MSP430F6779 , MSP430F67791 , MSP430F67791A , MSP430F6779A
In the MSP430F67xxA devices, a RTCLOCK feature has been added to reduce the amount of reconfigurations that are necessary after a reset. The RTCLOCK feature is enabled by setting the RTCLOCK bit in the RTC's RTCCTL3 register. By setting this bit, it locks all LPM3.5 retention logic from write and reset operations as long as a power cycle on AUXVCC3 does not occur. This locking mechanism is accomplished by having LPM3.5 retention logic either locked or powered from AUXVCC3 instead of VDSYS. One thing to note is that if RTCLOCK is set, the configuration of the bits locked by RTCLOCK may be held but not the bits themselves (i.e. the value of affected bits in the debugger may not reflect the actual configuration when the RTCLOCK feature is enabled). RTCLOCK may need to even be reset before reinitialization of some RTC registers such as the RTC time and date registers.
One benefit of this RTCLOCK feature is that it prevents having to clear the RTCHOLD bit after a POR reset. This prevents the RTC from being stopped when exposed to a pulse on VCC that is long enough to set the RTCHOLD bit but not long enough to allow software to clear RTCHOLD. For instance, if a battery is connected to AUXVCC3 only, AUXVCC1 and AUXVCC2 are not used as alternative power supplies, and power is lost at DVCC/AVCC, the RTC would still continue to count. However, when power is restored, a POR event would occur and the RTCHOLD bit would automatically be set causing the RTC to be turned OFF. This RTCHOLD bit should be cleared as soon as possible so that the RTC can continue counting from where it was before RTCHOLD was set. As a result of having to turn off RTCHOLD, the RTC time is off by the time difference between when the RTCHOLD bit was set and when it was cleared in software. Additionally, there could be a case where power at DVCC/AVCC is restored long enough so that RTCHOLD is set but not long enough for the software to clear this bit, thereby causing the RTC to stop. However, with the RTCLOCK feature there is no need to clear the RTCHOLD bit, thereby preventing this from happening.
When using the RTCLOCK feature, the RTCLOCK bit should be set after RTCHOLD is cleared to allow the RTC to start counting. For a code example that shows how to use the RTCLOCK bit, refer to the TI Design Battery Management and Auxiliary Power Supply Options for E-Meters (TIDM-AUX-MODULE).