3 Sequencing

Powering the FET on and off in a controlled routine is necessary to prevent the V_GS voltage from being too high when the V_D is applied. Such a state causes the FET to operate in saturation mode, and thermal damage the FET or board that it is mounted on. Powering on a FET requires the following steps:

1. The first signal to be applied to the FET must be V_GS. The V_GS voltage must transition to the V_GS pinch-off voltage or lower. This ensures that when the V_D voltage is applied, the gate is already low.
2. Next, the drain voltage supply can be enabled, allowing the V_D to be powered to the nominal value (50 V, for example). Remember that as the V_GS is at the pinch-off voltage, I_DS must be minimal.
3. Now that the V_D is applied, the V_GS bias voltage can be increased to set the desired power output of the PA.
4. Finally, the RF signal can be enabled. This allows the FET to transmit a signal.

Figure 3-1 GaN Power Sequencing

The PA can be safely shut down by reversing the power-on steps.

1. Disable the RF signal from the FET.
2. Reduce the V_GS voltage to the pinch-off value, eliminating the power output of the FET.
3. Disable the V_D voltage by sending a disable signal to the drain supply.
4. Finally, the V_GS voltage can be allowed to collapse to ground as the PA is fully disabled.