Design Notes

The DACx3701 10-Bit and 8-Bit, Voltage-Output Smart DACs With Nonvolatile Memory and PMBus™ Compatible I2C Interface With GPI Control Data Sheet recommends using a 100-nF decoupling capacitor for the VDD pin and a 1.5-µF or greater bypass capacitor for the CAP pin. The CAP pin is connected to the internal LDO. Place these capacitors close to the device pins.
An external reference of 1.8V to 5.5V can be applied to the VDD pin of the device. In addition, there is an internal precision 1.21-V reference with ×1.5, ×2, ×3, and ×4 gain options. When using VDD as a reference, noise on VDD is directly translated to noise on the triangular waveform produced by the DAC53701. This noise is ratiometric to the voltage applied to the FB pin.
In this design, the 5-V VDD supply input is used as the reference. The duty cycle of the PWM output is decided by the high- and low-voltage levels of the triangular waveform, and the voltage applied to the FB pin of the DAC53701 (V_FB):
Equation 1.
Values of 4V and 1V are used for V_{TRIANGLE_HIGH} and V_{TRIANGLE_LOW} to avoid zero-code and full-scale errors. With an example V_FB of 2.5V and unity gain, the equation becomes:
Equation 1.
The DAC codes for V_{TRIANGLE_HIGH} and V_{TRIANGLE_LOW} are stored in the DAC_MARGIN_HIGH and DAC_MARGIN_LOW registers. The codes programmed to these registers, in decimal, are calculated using:
Equation 1.
Equation 1.
The equation becomes:
Equation 1.
Equation 1.
This is rounded to 819d and 205d to give a V_{TRIANGLE_HIGH} of 3.999V and V_{TRIANGLE_LOW} of 1V.
The frequency of the PWM output is equal to the frequency of the triangular waveform. This is calculated by:
Equation 1.
SLEW_RATE and CODE_STEP are selected in the GENERAL_CONFIG Register. A CODE_STEP of 8 least significant bits (LSBs) and SLEW_RATE of 32μs per code step can be selected to produce a frequency of 203.25Hz:
Equation 1.
Using a 5-V reference and the 10-bit DAC53701, the LSB size, or step size between each code, is about 4.88mV. Using lower reference voltages decreases the LSB size and thus increases the resolution of the MARGIN_HIGH and MARGIN_LOW voltages.
In this design, GPI0 is used for the Power-Up, Down (10kΩ) function. A high start pulse must be applied to GPI0 to power-on the DAC53701. The function of GPI0 can be modified in the GPI_CONFIG field of the CONFIG2 register.
GPI1 and GPI2 along with R_1–4 determine the voltage at V_FB. GPI1 and GPI2 toggle between 0 and VDD which changes the values in the resistor divider created by the different parallel combinations of resistors R_1–4. For example, when GPI1 and GPI2 are both off, R_2-4 are added in parallel, and create a resistor divider with R₁. If the digital values applied to GPI1 and GPI2 are different from VDD or ground, MOSFETs can be added as level translators to each GPI.
The DAC53701 can be programmed with the initial register settings described in the Register Settings section using I2C. The initial register settings can be saved in the NVM by writing a 1 to the NVM_PROG field of the TRIGGER register. After programming the NVM, the device loads all applicable registers with the values stored in the NVM after a reset or a power cycle.