SLAAE47A May 2022 – August 2022 DAC11001A , DAC11001B

6 Error Summary

Total error for this DAC circuit topology can be calculated using root-sum-square method or worst-case error method. Assuming all the error sources are not correlated to each other, we can calculate the total error as follows.

Equation 16.

T o t a l E r r o r = \sqrt{{V r e f E r r o r}^{2} + {D A C E r r o r}^{2} + {N o n I n v e r t i n g A m p E r r o r}^{2} + {I n v e r t i n g A m p E r r o r}^{2} + . . . . . . . .}

Table 6-1 Total Error Calculations

Error Contribution	Error in ppm
DAC11001A	57.95
Voltage Reference (REF6025)	525
Non Inverting Amplifier (OPA828)	532.05
Inverting Amplifier (OPA828)	303.66
Reference Buffer (Both inverting and non inverting stages)	215.38
DAC output buffer (OPA828)	76.2
Total	840.65

As shown in Table 6-1, it is clear that the total error in the 20-bit DAC system is dominated by the reference amplifier and the buffer section. DAC11001A contributes approximately 4% of the total error in the system.

Figure 6-1 Error Distribution Pie Chart

Table 6-2 Design Featured Devices

Device	Key features	Link
DAC11001A	DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast Settling, High-Voltage Output, Digital-to-Analog Converters (DA	DAC11001A
OPA828	OPA828 Low-Offset, Low-Drift, Low-Noise, 45-MHz, 36-V JFET-Input, RRO Operational Amplifier	OPA828
REF6025	REF60xx High-Precision Voltage Reference With Integrated ADC Drive Buffer	REF6025