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SLAAE47A May 2022 – August 2022 DAC11001A , DAC11001B

Abstract
Trademarks
1Introduction
2DAC Error Sources
3Error Sources from Reference
4Error Sources from Inverting and Non-Inverting Gain Stage
5Example Calculation using DAC11001A
6Error Summary
7References
8Revision History

4.1 Input Offset Voltage Error

Input offset voltage, V_IO, is defined as the DC voltage that must be applied between the input terminals to force the quiescent DC output voltage to zero or some other level, if specified. If the input stage was perfectly symmetrical and the transistors were perfectly matched, V_IO = 0 V.

Equation 9.

I n p u t o f f s e t V o l a t g e E r r o r (p p m) = \frac{V_{o s} (m a x) (V) \times O f f s e t V o l t a g e G a i n}{| (O p a m p^{'} s O u t p u t V o l a t g e) (V) |}

where,

Equation 10.

O f f s e t V o l t a g e G a i n = 1 + \frac{R_{f}}{R_{g}}

Where R_f and R_g are the feedback and the gain setting registers respectively. Above equation is valid for both inverting and non-inverting amplifier stages.