SLAAE47A May   2022  – August 2022 DAC11001A , DAC11001B

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2DAC Error Sources
    1. 2.1 Offset Error
    2. 2.2 Gain Error
    3. 2.3 Integral Non Linearity (INL)
    4. 2.4 Noise Sources
  5. 3Error Sources from Reference
    1. 3.1 Initial Accuracy
    2. 3.2 Temperature Drift
    3. 3.3 Load Regulation Error
    4. 3.4 Line Regulation Error
    5. 3.5 0.1 - 10 Hz Peak-to-Peak Noise
    6. 3.6 Example Using REF7025
  6. 4Error Sources from Inverting and Non-Inverting Gain Stage
    1. 4.1 Input Offset Voltage Error
    2. 4.2 Input Offset Voltage Drift Error
    3. 4.3 Power Supply Rejection Ratio (PSRR) Error
    4. 4.4 Open Loop Gain Error
    5. 4.5 Resistor Tolerance Error
  7. 5Example Calculation using DAC11001A
  8. 6Error Summary
  9. 7References
  10. 8Revision History

Resistor Tolerance Error

This error refers to the gain error caused by the tolerance of the gain setting resistors. This is one of the major contributors of error in any amplifier design. \ and Equation 15 can be used to calculate the error due to resistor tolerances for both the non-inverting and inverting gain stages.

Equation for non-inverting stage:

Equation 14. Resistor Tolerance Errorppm= 1 + Rf()×1+ Tolerance%100Rg×1 - Tolerance%100 - Abs  1 + RfRgAbs 1 + RfRg×106

Equation for inverting stage:

Equation 15. Resistor Tolerance Errorppm= 1 + Rf×1+ Tolerance%100Rg×1 - Tolerance%100 - Abs  - RfRgAbs - RfRg×106