SLAS538B October   2007  – November 2016 TLV320AIC34

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hardware Reset
      2. 9.3.2  I2C Bus Debug In A Glitched System
      3. 9.3.3  Digital Audio Data Serial Interface
      4. 9.3.4  TDM Data Transfer
      5. 9.3.5  Audio Data Converters
      6. 9.3.6  Audio Clock Generation
      7. 9.3.7  Stereo Audio ADC
        1. 9.3.7.1 Stereo Audio ADC High-pass Filter
      8. 9.3.8  Digital Audio Processing For Record Path
      9. 9.3.9  Automatic Gain Control (AGC)
      10. 9.3.10 Stereo Audio DAC
      11. 9.3.11 Digital Audio Processing For Playback
      12. 9.3.12 Digital Interpolation Filter
      13. 9.3.13 Delta-Sigma Audio DAC
      14. 9.3.14 Audio DAC Digital Volume Control
      15. 9.3.15 Increasing DAC Dynamic Range
      16. 9.3.16 Analog Output Common-Mode Adjustment
      17. 9.3.17 Audio DAC Power Control
      18. 9.3.18 Audio Analog Inputs
      19. 9.3.19 Analog Input Bypass Path Functionality
      20. 9.3.20 ADC PGA Signal Bypass Path Functionality
      21. 9.3.21 Input Impedance and VCM Control
      22. 9.3.22 Passive Analog Bypass During Power Down
      23. 9.3.23 MICBIAS_x Generation
      24. 9.3.24 Digital Microphone Connectivity
      25. 9.3.25 Analog Fully Differential Line Output Drivers
      26. 9.3.26 Analog High-Power Output Drivers
      27. 9.3.27 Short-Circuit Output Protection
      28. 9.3.28 Jack or Headset Detection
      29. 9.3.29 Output Stage Volume Controls
    4. 9.4 Device Functional Modes
      1. 9.4.1 I2C Control Mode
      2. 9.4.2 Right-Justified Mode
      3. 9.4.3 Left-Justified Mode
      4. 9.4.4 I2S Mode
      5. 9.4.5 DSP Mode
    5. 9.5 Programming
      1. 9.5.1 Digital Control Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Register Description
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
DRVDD to AVSS_ADC, AVDD_DAC to AVSS_DAC –0.3 3.9 V
DRVDD to DRVSS –0.3 3.9 V
IOVDD to DVSS –0.3 3.9 V
DVDD to DVSS –0.3 2.5 V
AVDD_DAC to DRVDD –0.1 0.1 V
Digital input voltage to DVSS –0.3 IOVDD + 0.3 V
Analog input voltage to AVSS_ADC, AVSS_DAC –0.3 AVDD_DAC + 0.3 V
Power dissipation (TJ Max – TA) / RθJA
Junction temperature, TJ 105 °C
Operating temperature, TA –40 85 °C
Storage temperature, Tstg –65 105 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD_DAC, DRVDD(1) Analog supply voltage 2.7 3.3 3.6 V
DVDD(1) Digital core supply voltage 1.65 1.8 1.95 V
IOVDD(1) Digital I/O supply voltage 1.1 1.8 3.6 V
AVDD_DAC Analog full-scale 0-dB input voltage (DRVDD = 3.3 V) 0.707 VRMS
Stereo line output load resistance (codec block A and codec block B) 10 kΩ
Stereo headphone output load resistance
(codec block A and codec block B)		 16 Ω
Stereo speaker output load resistance (codec block A ONLY) 8 Ω
Digital output load capacitance 10 pF
TA Operating free-air temperature –40 85 °C
(1) Analog voltage values are with respect to AVSS_ADC, AVSS_DAC, DRVSS; digital voltage values are with respect to DVSS.

8.4 Thermal Information

THERMAL METRIC(1) TLV320AIC34 UNIT
ZAS (NFBGA)
87 PINS
RθJA Junction-to-ambient thermal resistance 53.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 16.3 °C/W
RθJB Junction-to-board thermal resistance 25.3 °C/W
ψJT Junction-to-top characterization parameter 3 °C/W
ψJB Junction-to-board characterization parameter 26.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

8.5 Electrical Characteristics

At 25°C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48-kHz, and 16-bit audio data (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO ADC – CODEC BLOCK A, B
Input signal level (0-dB) Single-ended input 0.707 VRMS
SNR Signal-to-noise ratio(1)(2) fS = 48 ksps, 0-dB PGA gain, LINE1LP_x and LINE1LM_x inputs ac-shorted to ground, A-weighted 80 92 dB
Dynamic range(2) fS = 48 ksps, 0-dB PGA gain, –60-dB full-scale input signal applied at LINE1LP_x and LINE1LM_x inputs, A-weighted 93 dB
THD Total harmonic distortion fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale 1-kHz input signal applied at LINE1LP_x and LINE1LM_x inputs –87 –70 dB
PSRR Power supply rejection ratio 217-Hz signal applied to DRVDD 49 dB
1-kHz signal applied to DRVDD 46
Gain error fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale 1-kHz input signal applied on LINE1LP_x and LINE1LM_x inputs 0.55 dB
Input channel separation 1-kHz, –2-dB full-scale signal, MIC3L_x to MIC3R_x –86 dB
1-kHz, –2-dB full-scale signal, MIC2LP_x and MIC2LM_x to MIC2RP_x and MIC2RM_x –98
1-kHz, –2-dB full-scale signal, MIC1LP_x and MIC1LM_x to MIC1RP_x and MIC1RM_x –80
ADC programmable-gain amplifier maximum gain 1-kHz input frequency, RSOURCE < 50 Ω 59.5 dB
ADC programmable-gain amplifier step size 1-kHz input frequency, RSOURCE < 50 Ω 0.5 dB
Input resistance LINE1LP_x, LINE1LM_x, or LINE1RP_x, LINE1RM_x inputs routed to single ADC;
input mix attenuation = 0 dB		 20 kΩ
LINE1LP_x, LINE1LM_x, or LINE1RP_x, LINE1RM_x inputs routed to single ADC; input mix attenuation = 12 dB 80
LINE2LP_x, LINE2LM_x, or LINE2RP_x, LINE2RM_x inputs routed to single ADC;
input mix attenuation = 0 dB		 20
LINE2LP_x, LINE2LM_x, or LINE2RP_x, LINE2RM_x inputs routed to single ADC; input mix attenuation = 12 dB 80
MIC3L_x or MIC3R_x inputs routed to single ADC,
input mix attenuation = 0 dB		 20
MIC3L_x or MIC3R_x inputs routed to single ADC, input mix attenuation = 12 dB 80
Input level control minimum attenuation setting 0 dB
Input level control maximum attenuation setting 12 dB
Input signal level Differential input 1.414 VRMS
SNR Signal-to-noise ratio(1)(2) fS = 48 ksps, 0-dB PGA gain, inputs ac-shorted to ground, differential mode, A-weighted 92 dB
THD Total harmonic distortion fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale 1-kHz input signal, differential mode, A-weighted –89 dB
ANALOG PASS-THROUGH MODE – CODEC BLOCK A, B
rds(on) Input-to-output switch resistance MIC1/LINE1 to LINE_OUT 330 Ω
MIC2/LINE2 to LINE_OUT 330
ADC DIGITAL DECIMATION FILTER, fS = 48 kHz – CODEC BLOCK A, B
Filter gain from 0 to 0.39 fS ±0.1 dB
Filter gain at 0.4125 fS –0.25 dB
Filter gain at 0.45 fS –3 dB
Filter gain at 0.5 fS –17.5 dB
Filter gain from 0.55 fS to 64 fS –75 dB
Filter group delay 17/fS s
MICROPHONE BIAS – CODEC BLOCK A, B
Bias voltage Programmable setting = 2 V, load current = 4 mA 2 V
Programmable setting = 2.5 V, load current = 4 mA 2.3 2.4 2.7
Programmable setting = DRVDD (3.3 V), load current = 4 mA 3
Current sourcing Programmable setting = 2.5 V 4 mA
AUDIO DAC – DIFFERENTIAL LINE OUTPUT, LOAD = 10 kΩ – CODEC BLOCK A, B
Full-scale output voltage 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 1.414 VRMS
SNR Signal-to-noise ratio(3) No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted 90 99 dB
Dynamic range –60 dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted 95 dB
THD Total harmonic distortion 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz –88 –75 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to AVDD_DAC 77 dB
1-kHz signal applied to AVDD_DAC 73
DAC channel separation 0-dB full-scale input signal between left and right lineout 123 dB
DAC gain error 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz –0.49 dB
AUDIO DAC – SINGLE-ENDED LINE OUTPUT, LOAD = 10 kΩ – CODEC BLOCK A, B
Full-scale output voltage 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 0.707 Vrms
SNR Signal-to-noise ratio No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted 94 dB
THD Total harmonic distortion 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz 79 dB
DAC gain error 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz –0.5 dB
AUDIO DAC – SINGLE-ENDED HEADPHONE OUTPUT, LOAD = 16 Ω – CODEC BLOCK A, B
Full-scale output voltage 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 0.707 Vrms
SNR Signal-to-noise ratio No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted 93 dB
No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, 50% DAC current boost, A-weighted 94 dB
Dynamic range –60 dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted 89 dB
THD Total harmonic distortion 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz –74 –65 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD, AVDD_DAC 41 dB
1-kHz signal applied to DRVDD, AVDD_DAC 44
DAC channel separation 0-dB full-scale input signal between left and right headphone out 84 dB
DAC gain error 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz –0.8 dB
AUDIO DAC – LINEOUT AND HEADPHONE OUT DRIVERS – CODEC BLOCK A, B
Output common mode First option 1.35 V
Second option 1.5
Third option 1.65
Fourth option 1.8
Output volume-control maximum setting 9 dB
Output volume-control step size 1 dB
AUDIO DAC – DIFFERENTIAL SPEAKER OUTPUT, RLOAD = 8 Ω, 1 kHz INPUT SIGNAL – CODEC BLOCK A ONLY
Full-scale output voltage, codec block A only 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 1.414 VRMS
SNR Signal-to-noise ratio, codec block A only A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, output common-mode setting = 1.35 V 96 dB
THD Total harmonic distortion, codec block A only fS = 48 kHz, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V –67 dB
DAC gain error, codec block A only fS = 48 kHz, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V –2 dB
DAC DIGITAL INTERPOLATION, FILTER fS = 48-ksps – CODEC BLOCK A, B
Pass band 0 0.45 fS Hz
Pass-band ripple ±0.06 dB
Transition band 0.45 fS 0.55 fS Hz
Stop band 0.55 fS 7.5 fS Hz
Stop-band attenuation 65 dB
Group delay 21 / fS s
DIGITAL I/O – CODEC BLOCK A, B
VIL Input low level –0.3 0.3 IOVDD V
VIH Input high level(4) IOVDD > 1.6 V 0.7 IOVDD V
IOVDD < 1.6 V 1.1
VOL Output low level 0.1 IOVDD V
VOH Output high level 0.8 IOVDD V
POWER CONSUMPTION, DRVDD, AVDD_DAC = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V – CURRENTS LISTED FOR CODEC BLOCK A OR BLOCK B
IIN IDRVDD + IAVDD_DAC RESET_x pulse applied, no external clocks 1.19 µA
IDVDD RESET_x pulse applied, no external clocks 0.75
IDRVDD + IAVDD_DAC Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal, PLL off 2.06 mA
IDVDD Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal, PLL off 0.55
IDRVDD + IAVDD_DAC Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal, PLL off 4.06
IDVDD Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal, PLL off 0.67
IDRVDD + IAVDD_DAC Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no signal, PLL off 4.27
IDVDD Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no signal, PLL off 2.45
IDRVDD + IAVDD_DAC Stereo DAC playback to lineout, analog mixer bypassed, fS = 48 ksps, I2S slave, no signal, PLL off 3.5
IDVDD Stereo DAC playback to lineout, analog mixer bypassed, fS = 48 ksps, I2S slave, no signal, PLL off 2.3
IDRVDD + IAVDD_DAC Stereo DAC playback to Lineout, fS = 48 ksps, I2S slave, no signal, PLL off 4.42
IDVDD Stereo DAC playback to Lineout, fS = 48 ksps, I2S slave, no signal, PLL off 2.27
IDRVDD + IAVDD_DAC Stereo DAC playback to stereo single-ended headphones, fS = 48 ksps, I2S slave, no signal, PLL off 7.78
IDVDD Stereo DAC playback to stereo single-ended headphones, fS = 48 ksps, I2S slave, no signal, PLL off 2.26
IDRVDD + IAVDD_DAC Stereo linein to stereo lineout, no signal 3.16
IDVDD Stereo linein to stereo lineout, no signal 1.79
IDRVDD + IAVDD_DAC Extra power when PLL enabled 1.2
IDVDD Extra power when PLL enabled 1
IDRVDD + IAVDD_DAC All blocks powered down, headset detection enabled 5.3 µA
IDVDD All blocks powered down, headset detection enabled 188
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic-range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16-Ω single-ended load.
(4) When IOVDD < 1.6 V, minimum VIH is 1.1 V.

8.6 Timing Requirements

For A and B interfaces, all specifications at 25°C and DVDD = 1.8 V (unless otherwise noted)(1)
MIN NOM MAX UNIT
I2S, LJF, RJF TIMING IN MASTER MODE (SEE Figure 1)
td(WS) ADWS/WCLK_x delay time IOVDD = 1.1 V 50 ns
IOVDD = 3.3 V 15
td(DO-WS) ADWS/WCLK_x to DOUT_x delay time IOVDD = 1.1 V 50 ns
IOVDD = 3.3 V 20
td(DO-BCLK) BCLK_x to DOUT_x delay time IOVDD = 1.1 V 50 ns
IOVDD = 3.3 V 15
ts(DI) DIN_x setup time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
th(DI) DIN_x hold time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
tr Rise time IOVDD = 1.1 V 30 ns
IOVDD = 3.3 V 10
tf Fall time IOVDD = 1.1 V 30 ns
IOVDD = 3.3 V 10
DSP TIMING IN MASTER MODE (SEE Figure 2)
td(WS) ADWS/WCLK_x delay time IOVDD = 1.1 V 50 ns
IOVDD = 3.3 V 15
td(DO-BCLK) BCLK_x to DOUT_x delay time IOVDD = 1.1 V 50 ns
IOVDD = 3.3 V 15
ts(DI) DIN_x setup time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
th(DI) DIN_x hold time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
tr Rise time IOVDD = 1.1 V 30 ns
IOVDD = 3.3 V 10
tf Fall time IOVDD = 1.1 V 30 ns
IOVDD = 3.3 V 10
I2S, LJF, RJF TIMING IN SLAVE MODE (SEE Figure 3)
tH(BCLK) BCLK_x high period IOVDD = 1.1 V 70 ns
IOVDD = 3.3 V 35
tL(BCLK) BCLK_x low period IOVDD = 1.1 V 70 ns
IOVDD = 3.3 V 35
ts(WS) ADWS/WCLK_x setup time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
th(WS) ADWS/WCLK_x hold time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
td(DO-WS) ADWS/WCLK_x to DOUT_x delay time
(for LJF mode only)		 IOVDD = 1.1 V 50 ns
IOVDD = 3.3 V 20
td(DO-BCLK) BCLK_x to DOUT_x delay time IOVDD = 1.1 V 50 ns
IOVDD = 3.3 V 20
ts(DI) DIN_x setup time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
th(DI) DIN_x hold time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
tr Rise time IOVDD = 1.1 V 8 ns
IOVDD = 3.3 V 4
tf Fall time IOVDD = 1.1 V 8 ns
IOVDD = 3.3 V 4
DSP TIMING IN SLAVE MODE (SEE Figure 4)
tH(BCLK) BCLK_x high period IOVDD = 1.1 V 70 ns
IOVDD = 3.3 V 35
tL(BCLK) BCLK_x low period IOVDD = 1.1 V 70 ns
IOVDD = 3.3 V 35
ts(WS) ADWS/WCLK_x setup time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
th(WS) ADWS/WCLK_x hold time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
td(DO-BCLK) BCLK_x to DOUT_x delay time IOVDD = 1.1 V 50 ns
IOVDD = 3.3 V 20
ts(DI) DIN_x setup time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
th(DI) DIN_x hold time IOVDD = 1.1 V 10 ns
IOVDD = 3.3 V 6
tr Rise time IOVDD = 1.1 V 6 ns
IOVDD = 3.3 V 4
tf Fall time IOVDD = 1.1 V 6 ns
IOVDD = 3.3 V 4
(1) All timing specifications are measured at characterization but not tested at final test.
TLV320AIC34 t0145-04_las538.gif Figure 1. I2S, LJF, RJF Timing in Master Mode
TLV320AIC34 t0146-03_las538.gif Figure 2. DSP Timing in Master Mode
TLV320AIC34 t0145-05_las538.gif Figure 3. I2S, LJF, RJF Timing in Slave Mode
TLV320AIC34 t0146-04_las538.gif Figure 4. DSP Timing in Slave Mode

8.7 Typical Characteristics

 

TLV320AIC34 thd1_op_las509.gif Figure 5. Total Harmonic Distortion
vs Headphone Out Power
TLV320AIC34 mbias_v_las509.gif Figure 7. MICBIAS_x Voltage vs Supply Voltage
TLV320AIC34 snr_adc_las509.gif Figure 6. Signal-to-Noise Ratio
vs ADC PGA Setting
TLV320AIC34 mbias_ta_las509.gif Figure 8. MICBIAS_x Voltage
vs Free-Air Temperature
TLV320AIC34 l_dac_fft_las509.gif Figure 9. Left-DAC FFT
TLV320AIC34 l_adc_fft_las509.gif Figure 11. Left-ADC FFT
TLV320AIC34 r_dac_fft_las509.gif Figure 10. Right-DAC FFT
TLV320AIC34 r_adc_fft_las509.gif Figure 12. Right-ADC FFT
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