8.4.5 Serial Peripheral Interface (SPI)

The serial port of the DAC38RF82 (or DAC38RF89) is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of DAC38RF82 (or DAC38RF89). It is compatible with most synchronous transfer formats and can be configured as a 3 or 4 terminal interface by SIF4_ENA in register IO_CONFIG (8.5.2). In both configurations, SCLK is the serial interface input clock and SDEN is serial interface enable. For 3 terminal configuration, SDIO is a bidirectional terminal for both data in and data out. For 4 terminal configuration, SDIO is bidirectional and SDO is data out only. Data is input into the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

The SPI registers are reset by writing a 1 to SPI_RESET in register RESET_CONFIG (8.5.1).

Each read/write operation is framed by signal SDEN (Serial Data Enable Bar) asserted low. The first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit address to be accessed. Figure 50 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. The data transfer cycle consists of two bytes.

Figure 51 shows the serial interface timing diagram for a DAC38RF82 (or DAC38RF89) write operation. SCLK is the serial interface clock input to DAC38RF82 (or DAC38RF89). Serial data enable SDEN is an active low input to DAC38RF82 (or DAC38RF89). SDIO is serial data input. Input data to DAC38RF82 (or DAC38RF89) is clocked on the rising edges of SCLK.

Figure 51. Serial Interface Write Timing Diagram

Figure 52 shows the serial interface timing diagram for a DAC38RF82 (or DAC38RF89) read operation. SCLK is the serial interface clock input to DAC38RF82 (or DAC38RF89). Serial data enable SDEN is an active low input to DAC38RF82 (or DAC38RF89). SDIO is serial data input during the instruction cycle. In 3 pin configuration, SDIO is data out from the DAC38RF82 (or DAC38RF89) during the data transfer cycle, while SDO is in a high-impedance state. In 4 pin configuration, both SDIO and SDO are data out from the DAC38RF82 (or DAC38RF89) during the data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the final falling edge of SCLK until the rising edge of SDEN when they will 3-state.

Figure 52. Serial Interface Read Timing Diagram

n the SIF interface there are four types of registers: