SLASEB7D June 2017 – December 2020
PRODUCTION DATA
- 1 Features
- 2 Applications
- 3 Description
- 4 Functional Block Diagrams
- 5 Revision History
- 6 Device Comparison
- 7 Terminal Configuration and Functions
-
8 Specifications
- 8.1 Absolute Maximum Ratings
- 8.2 ESD Ratings
- 8.3 Recommended Operating Conditions
- 8.4 Active Mode Supply Current Into VCC Excluding External Current
- 8.5 Typical Characteristics, Active Mode Supply Currents
- 8.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
- 8.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
- 8.8 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
- 8.9 Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
- 8.10 Typical Characteristics, Low-Power Mode Supply Currents
- 8.11 Typical Characteristics, Current Consumption per Module (1)
- 8.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
- 8.13
Timing and Switching Characteristics
- 8.13.1 Power Supply Sequencing
- 8.13.2 Reset Timing
- 8.13.3 Clock Specifications
- 8.13.4 Wake-up Characteristics
- 8.13.5 Digital I/Os
- 8.13.6 LEA
- 8.13.7 Timer_A and Timer_B
- 8.13.8
eUSCI
- 8.13.8.1 eUSCI (UART Mode) Clock Frequency
- 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
- 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
- 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
- 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
- 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
- 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
- 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
- 8.13.8.9 eUSCI (SPI Slave Mode) Timing Diagrams
- 8.13.9 Segment LCD Controller
- 8.13.10
ADC12_B
- 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
- 8.13.10.2 12-Bit ADC, Timing Parameters
- 8.13.10.3 12-Bit ADC, Linearity Parameters
- 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
- 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
- 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
- 8.13.10.7 12-Bit ADC, External Reference
- 8.13.10.8 Temperature Sensor Typical Characteristics
- 8.13.11 Reference
- 8.13.12 Comparator
- 8.13.13 FRAM
- 8.13.14 USS
- 8.13.15 Emulation and Debug
-
9 Detailed Description
- 9.1 Overview
- 9.2 CPU
- 9.3 Ultrasonic Sensing Solution (USS) Module
- 9.4 Low-Energy Accelerator (LEA) for Signal Processing
- 9.5 Operating Modes
- 9.6 Interrupt Vector Table and Signatures
- 9.7 Bootloader (BSL)
- 9.8 JTAG Operation
- 9.9 FRAM Controller A (FRCTL_A)
- 9.10 RAM
- 9.11 Tiny RAM
- 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
- 9.13
Peripherals
- 9.13.1 Digital I/O
- 9.13.2 Oscillator and Clock System (CS)
- 9.13.3 Power-Management Module (PMM)
- 9.13.4 Hardware Multiplier (MPY)
- 9.13.5 Real-Time Clock (RTC_C)
- 9.13.6 Measurement Test Interface (MTIF)
- 9.13.7 Watchdog Timer (WDT_A)
- 9.13.8 System Module (SYS)
- 9.13.9 DMA Controller
- 9.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
- 9.13.11 TA0, TA1, and TA4
- 9.13.12 TA2 and TA3
- 9.13.13 TB0
- 9.13.14 ADC12_B
- 9.13.15 USS
- 9.13.16 Comparator_E
- 9.13.17 CRC16
- 9.13.18 CRC32
- 9.13.19 AES256 Accelerator
- 9.13.20 True Random Seed
- 9.13.21 Shared Reference (REF)
- 9.13.22 LCD_C
- 9.13.23 Embedded Emulation
- 9.14
Input/Output Diagrams
- 9.14.1 Port Function Select Registers (PySEL1 , PySEL0)
- 9.14.2 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
- 9.14.3 Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
- 9.14.4 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
- 9.14.5 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
- 9.14.6 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
- 9.14.7 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
- 9.14.8 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
- 9.14.9 Port P6 (P6.0) Input/Output With Schmitt Trigger
- 9.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
- 9.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
- 9.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
- 9.14.13 Port P7 (P7.4) Input/Output With Schmitt Trigger
- 9.14.14 Port P7 (P7.5) Input/Output With Schmitt Trigger
- 9.14.15 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
- 9.14.16 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
- 9.14.17 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
- 9.14.18 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
- 9.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
- 9.14.20 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
- 9.14.21 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
- 9.15 Device Descriptors (TLV)
- 9.16 Memory Map
- 9.17 Identification
-
10Applications, Implementation, and Layout
- 10.1
Device Connection and Layout Fundamentals
- 10.1.1 Power Supply Decoupling and Bulk Capacitors
- 10.1.2 External Oscillator (HFXT and LFXT)
- 10.1.3 USS Oscillator (USSXT)
- 10.1.4 Transducer Connection to the USS Module
- 10.1.5 Charge Pump Control of Input Multiplexer
- 10.1.6 JTAG
- 10.1.7 Reset
- 10.1.8 Unused Pins
- 10.1.9 General Layout Recommendations
- 10.1.10 Do's and Don'ts
- 10.2 Peripheral- and Interface-Specific Design Information
- 10.1
Device Connection and Layout Fundamentals
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
9.6 Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address, and signatures are in the address range 0FFFFh to 0FF80h. Figure 9-2 summarizes the content of this address range.
Figure 9-2 Interrupt Vectors, Signatures and PasswordsThe power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing to the start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 9-4 shows the device-specific interrupt vector locations.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if enabled by the corresponding signature).
The signatures start at 0FF80h and extend to higher addresses. Signatures are evaluated during device start-up. Table 9-5 shows the device-specific signature locations.
A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses. The password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for the password. The length of the JTAG password depends on the JTAG signature.
See the chapter System Resets, Interrupts, and Operating Modes, System Control Module (SYS) in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.
Table 9-4 Interrupt Sources, Flags, and Vectors
| INTERRUPT SOURCE | INTERRUPT FLAG | INTERRUPT VECTOR REGISTER | SYSTEM INTERRUPT | WORD ADDRESS | PRIORITY |
|---|---|---|---|---|---|
| System Reset | SYSRSTIV(1) | Reset | 0FFFEh | Highest | |
| Power up, brownout, supply supervisor | SVSHIFG | ||||
| External reset, RST | PMMRSTIFG | ||||
| Watchdog time-out (watchdog mode) | WDTIFG | ||||
| WDT, FRCTL MPU, CS, PMM password violation | WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW | ||||
| FRAM uncorrectable bit error detection | UBDIFG | ||||
| MPU segment violation | MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG | ||||
| Software POR, BOR | PMMPORIFG, PMMBORIFG | ||||
| System NMI | SYSSNIV(1) | (Non)maskable(3) | 0FFFCh | ||
| Vacant memory access(2) | VMAIFG | ||||
| JTAG mailbox | JMBINIFG, JMBOUTIFG | ||||
| FRAM access time error | ACCTEIFG | ||||
| FRAM write protection error | WPIFG | ||||
| FRAM bit error detection | CBDIFG, UBDIFG | ||||
| MPU segment violation | MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG | ||||
| User NMI | SYSUNIV(1) | (Non)maskable(3) | 0FFFAh | ||
| External NMI | NMIIFG | ||||
| Oscillator fault | OFIFG | ||||
| LEA RAM access conflict | DACCESSIFG | ||||
| Comparator_E | CEIFG, CEIIFG, CERDYIFG | CEIV(1) | Maskable | 0FFF8h | |
| TB0 | TB0CCR0 CCIFG | Maskable | 0FFF6h | ||
| TB0 | TB0CCR1 CCIFG to TB0CCR6 CCIFG, TB0CTL.TBIFG | TB0IV(1) | Maskable | 0FFF4h | |
| Watchdog timer (interval timer mode) | WDTIFG | Maskable | 0FFF2h | ||
| eUSCI_A0 receive or transmit | UCRXIFG, UCTXIFG (SPI mode) | UCA0IV(1) | Maskable | 0FFF0h | |
| UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode) | |||||
| eUSCI_B0 receive or transmit | UCRXIFG, UCTXIFG (SPI mode) | UCB0IV(1) | Maskable | 0FFEEh | |
| UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode) | |||||
| ADC12_B(4) | ADC12IFG0 to ADC12IFG31, ADC12LOIFG, ADC12INIFG, ADC12HIIFG, ADC12RDYIFG, ADC21OVIFG, ADC12TOVIFG | ADC12IV(1) | Maskable | 0FFECh | |
| TA0 | TA0CCR0 CCIFG | Maskable | 0FFEAh | ||
| TA0 | TA0CCR1 CCIFG, TA0CCR2 CCIFG, TA0CTL.TAIFG | TA0IV(1) | Maskable | 0FFE8h | |
| eUSCI_A1 receive or transmit | UCRXIFG, UCTXIFG (SPI mode) | UCA1IV(1) | Maskable | 0FFE6h | |
| UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode) | |||||
| DMA | DMA0CTL.DMAIFG, DMA1CTL.DMAIFG, DMA2CTL.DMAIFG | DMAIV(1) | Maskable | 0FFE4h | |
| TA1 | TA1CCR0 CCIFG | Maskable | 0FFE2h | ||
| TA1 | TA1CCR1 CCIFG, TA1CCR2 CCIFG, TA1CTL.TAIFG | TA1IV(1) | Maskable | 0FFE0h | |
| I/O port P1 | P1IFG.0 to P1IFG.7 | P1IV(1) | Maskable | 0FFDEh | |
| TA2 | TA2CCR0 CCIFG | Maskable | 0FFDCh | ||
| TA2 | TA2CCR1 CCIFG, TA2CTL.TAIFG | TA2IV(1) | Maskable | 0FFDAh | |
| I/O port P2 | P2IFG.0 to P2IFG.7 | P2IV(1) | Maskable | 0FFD8h | |
| TA3 | TA3CCR0 CCIFG | Maskable | 0FFD6h | ||
| TA3 | TA3CCR1 CCIFG, TA3CTL.TAIFG | TA3IV(1) | Maskable | 0FFD4h | |
| I/O port P3 | P3IFG.0 to P3IFG.7 | P3IV(1) | Maskable | 0FFD2h | |
| I/O port P4 | P4IFG.0 to P4IFG.7 | P4IV(1) | Maskable | 0FFD0h | |
| LCD_C | LCDNOCAPIFG, LCDBLKOFFIFG, LCDBLKONIFG, LCDFRMIFG | LCDCIV(1) | Maskable | 0FFCEh | |
| RTC_C | RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG | RTCIV(1) | Maskable | 0FFCCh | |
| AES | AESRDYIFG | Maskable | 0FFCAh | ||
| TA4 | TA4CCR0 CCIFG | Maskable | 0FFC8h | ||
| TA4 | TA4CCR1 CCIFG, TA4CTL.TAIFG | TA4IV(1) | Maskable | 0FFC6h | |
| I/O port P5 | P5IFG.0 to P5IFG.7 | P5IV(1) | Maskable | 0FFC4h | |
| I/O port P6 | P6IFG.0 to P6IFG.7 | P6IV(1) | Maskable | 0FFC2h | |
| eUSCI_A2 receive or transmit | UCRXIFG, UCTXIFG (SPI mode) | UCA2IV(1) | Maskable | 0FFC0h | |
| UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode) | |||||
| eUSCI_A3 receive or transmit | UCRXIFG, UCTXIFG (SPI mode) | UCA3IV(1) | Maskable | 0FFBEh | |
| UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode) | |||||
| eUSCI_B1 receive or transmit | UCRXIFG, UCTXIFG (SPI mode) | UCB1IV(1) | Maskable | 0FFBCh | |
| UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode) | |||||
| I/O port P7 | P7IFG.0 to P7IFG.7 | P7IV(1) | Maskable | 0FFBAh | |
| I/O port P8 | P8IFG.0 to P8IFG.7 | P8IV(1) | Maskable | 0FFB8h | |
| I/O port P9 | P9IFG.0 to P9IFG.7 | P9IV(1) | Maskable | 0FFB6h | |
| LEA | CMDIFG, SDIIFG, OORIFG, TIFG, COVLIFG | LEAIV(1) | Maskable | 0FFB4h | |
| UUPS | PTMOUT, PREQIG | IIDX(1) | Maskable | 0FFB2h | |
| HSPLL | PLLUNLOCK | IIDX(1) | Maskable | 0FFB0h | |
| SAPH | DATAERR, TMFTO, SEQDN, PNGDN | IIDX(1) | Maskable | 0FFAEh | |
| SDHS | OVF, ACQDONE, SSTRG, DTRDY, WINHI, WINLO | IIDX(1) | Maskable | 0FFACh | Lowest |
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.
(4) Only on devices with ADC, otherwise reserved.
Table 9-5 Signatures
| SIGNATURE | WORD ADDRESS |
|---|---|
| IP Encapsulation Signature2 | 0FF8Ah |
| IP Encapsulation Signature1(1) | 0FF88h |
| BSL Signature2 | 0FF86h |
| BSL Signature1 | 0FF84h |
| JTAG Signature2 | 0FF82h |
| JTAG Signature1 | 0FF80h |
(1) Must not contain 0AAAAh if used as the JTAG password.