米6体育平台手机版

SLASEB7D June 2017 – December 2020

PRODUCTION DATA

8.13.5.2 Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage (see Figure 8-10 and Figure 8-11)	I_(OHmax) = –1 mA⁽¹⁾	2.2 V	V_CC – 0.25		V_CC	V
		I_(OHmax) = –3 mA⁽²⁾	2.2 V	V_CC – 0.60		V_CC
		I_(OHmax) = –2 mA⁽¹⁾	3.0 V	V_CC – 0.25		V_CC
		I_(OHmax) = –6 mA⁽²⁾	3.0 V	V_CC – 0.60		V_CC
V_OL	Low-level output voltage (see Figure 8-8 and Figure 8-9)	I_(OLmax) = 1 mA⁽¹⁾	2.2 V	V_SS		V_SS + 0.25	V
		I_(OLmax) = 3 mA⁽²⁾	2.2 V	V_SS		V_SS + 0.60
		I_(OLmax) = 2 mA⁽¹⁾	3.0 V	V_SS		V_SS + 0.25
		I_(OLmax) = 6 mA⁽²⁾	3.0 V	V_SS		V_SS + 0.60
f_Px.y	Port output frequency (with load)⁽⁵⁾	C_L = 20 pF, R_L ⁽³⁾ ⁽⁴⁾	2.2 V	16			MHz
f_Px.y	Port output frequency (with load)⁽⁵⁾	C_L = 20 pF, R_L ⁽³⁾ ⁽⁴⁾	3.0 V	16			MHz
f_{Port_CLK}	Clock output frequency⁽⁵⁾	ACLK, MCLK, or SMCLK at configured output port, C_L = 20 pF⁽⁴⁾	2.2 V	16			MHz
f_{Port_CLK}	Clock output frequency⁽⁵⁾		3.0 V	16			MHz
t_rise,dig	Port output rise time, digital only port pins	C_L = 20 pF	2.2 V		4	15	ns
t_rise,dig	Port output rise time, digital only port pins	C_L = 20 pF	3.0 V		3	15	ns
t_fall,dig	Port output fall time, digital only port pins	C_L = 20 pF	2.2 V		4	15	ns
t_fall,dig	Port output fall time, digital only port pins	C_L = 20 pF	3.0 V		3	15	ns
t_rise,ana	Port output rise time, port pins with shared analog functions	C_L = 20 pF	2.2 V		6	15	ns
t_rise,ana		C_L = 20 pF	3.0 V		4	15	ns
t_fall,ana	Port output fall time, port pins with shared analog functions	C_L = 20 pF	2.2 V		6	15	ns
t_fall,ana		C_L = 20 pF	3.0 V		4	15	ns

(1) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.

(2) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.

(3) A resistive divider with 2 × R1 and R1 = 1.6 kΩ between V_CC and V_SS is used as load. The output is connected to the center tap of the divider. C_L = 20 pF is connected from the output to V_SS.

(4) The output voltage reaches at least 10% and 90% V_CC at the specified toggle frequency.

(5) The port can output frequencies at least up to the specified limit, and the port might support higher frequencies.